Hi,
Is there any tool from Cadence that can report unused Verilog packages?
Often the import MyPackage::* statements are left at the top of a module declaration even though the code that was using them has been removed from the module. This causes unnecessary dependencies that may not be detected. So can I get a report of such unused packages from xmelab, JasperGold, Genus, or any other Cadence tool?
Thanks,
Max
