Hello,
I am using cadence Xcelium for simulation and as I run the elaboration step, i am seeing the following message and the simulation process stops -
xmelab: *W,LARGEM: Large VHDL memory (134217728 >= 2^25) declared (file: ahb_monitor.vhd, line: 62). You may hit system virtual memory exceeded issues.
xmelab: *F,INTERR: INTERNAL EXCEPTION
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The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: xmelab(64) 20.09-s006
HOSTNAME: rt-xicrh7-6
OPERATING SYSTEM: Linux 3.10.0-1160.41.1.el7.x86_64 #1 SMP Mon Aug 16 14:52:32 UTC 2021 x86_64
MESSAGE: cu_vhdl_sig_ptrblk_setdummysize(): Dummy sigsize setting botch
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csi-xmelab - CSI: Cadence Support Investigation, sending details to /projects/me158/me158aa/jps2rt/current/database_bosch_ip/gtm/sim_data/xmelab_27442.err
csi-xmelab - CSI: investigation complete, send /projects/me158/me158aa/jps2rt/current/database_bosch_ip/gtm/sim_data/xmelab_27442.err to Cadence Support
class AST_S_IF has parent of class AST_S_IF
xrun: *E,ELBERR: Error during elaboration (status 255), exiting.
TOOL: xrun(64) 20.09-s006: Exiting on Feb 09, 2022 at 11:11:24 CET (total: 00:01:35)
gmake: *** [makefile:151: compile_tb] Error 1
Any help on how to proceed would be appreciated.
Thank you.