Generation of EVCD file for Verilog-AMS

Hi,

Testbench developed in verilog-AMS and uses wreal as a ports and internal signals.

When It's tried to generate EVCD for design ports with $dumpports() gives error related to "Wreal is not supported".

I am using IUS 10.2 version. I need EVCD for vector generation for tester.

Please help me out.

Thanks in advance.

Regards,

Ankit