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the usage of e language "now"
hi all, i learn the code written by someone else has finished many years ago,and i couldn't contact with him.in the code ,i find the "now" programme,the defination and the example are easily...
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vcs_specman not created
Hi,I am trying to create an exe using vcs and specman,initially specman and vcs compilation went through fine and when the vcs simulation started i got an error saying as below,please let me know...
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OVM- Using interface to access DUT signals
Hi I am working under OVM based testbench and i would like to use status signals from the DUT in the data item - req (to make sure it is not in error state ). What is the way to do it? I would like to...
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Infineon CoolMOS Spice problem
Hello, i want to use an Infineon CoolMOS in a medium/high power switching application. The chip of choise is the IPD60R600E6. The spice model can be found...
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How to connect vPlan and your testbench
Hi guys, I've been exploring with the labs in UVM-SystemVerilog Workshop. The lab 1 to 5 are good, but lab 6 is sort of useless. It only shows me how to view the prewritten sessions and vplan. In the...
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Problem while integrating sv uvc in e environment
Hi Friends, I developed AHB arbiter UVC in sv by using UVM methodology. Now i want to verify my arbiter uvc with cadence ahb vip in e environment.while integrating i am facing error and then...
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Specman Tutorial
Hi everybody ,Can anybody please suggest me quickstart tutorial to specman-e . I have knowledge of systemverilog uvm and now i want to shift to specman e. I Have specman 9.2 and above... are there any...
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string macros in verilog AMS
Hello, Does anyone know how to define string macros in Verilogams? Today I have to do the following:`define display_value(str, sig) $display(“Value of signal %s is equal to %b”, str, sig) If I place...
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Specman/e: Flush sequence queue
Hello,I have started several sequences with the any_sequence.start_sequence() API on a driver to create a high datarate. Now I want to react on an exteranl event and flush all the remaining sequences...
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forcing the creation of a vcd file
Hello,How do I instruct simvision to force the creation of a vcd file? I am trying to create tcl script to dump signals into a vcd file and then immediately post-process this very vcd.These are the two...
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Add tcl script to tcl/tk Application Dashboard
Hi, I have created a small tcl script to modify the some properties on the Title Block. I wish to add the Script to the TCL/Tk Applications Dashboard.I followed the instructions in the...
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Error while trying to explore about get_inst_coverage
Hi, I'm trying to observe the difference between get_coverage & get_inst_coverage with the following example;class trans; rand logic wrd; rand logic [2:0] addr; rand logic [7:0] din; rand logic...
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merging the coverage from different testcase of the same DUT
Hi I am facing issue in the meging the code & functional coverage of the different testcase of the same dut commands used with iccr :==================================== set_dut_modules...
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latest e manual
hi,i used specman e in the past, and want to catch up.i could not find the latest e manual on cadence site. where can i find it?i do not have a specman installetion. is there an educational version i...
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simulation dump sliding window or start time
Hi all,I have a test case runs for long time and the error occurs at the end of the run. The dump is really big and it's very slow to open up the waveform. Does anyone knows the options how to start...
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I can't find "Part Manager" option in OrCad 16.3
Hy! Have you any idea, where is this "part manager" option from my OrCad 16.3? http://www.youtube.com/watch?v=AZRVEKfXfIcHere is my screenshot:...
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extract memory value in systemC
Hi all, I have 2 files. In file A.vhd, I model a memory using "type t_mem is array(conv_integer(BASE) to conv_integer(TOP-1)) of std_logic_vector(7 downto 0); variable mem : t_mem;".In file B.cpp,...
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Continue after failed PSL assertions
Hi!I am running a mixed-language simulation with irun. This includes PSL assertions in my VHDL code and SVA assertions in my SystemVerilog/UVM testbench.As the simulation runs in non-interactive mode...
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ncvlog: *E,EXPKWS - Error while running OVM env
Hi,ncvlog: *E,EXPKWS (../env/test.sv,4|29): Expecting port direction keyword 'input', 'output', 'inout', or 'ref'. (`define macro: ovm_field_utils_begin...
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Driving a circuit with spice models using verilog wreal stimulus
Hi All, I am running an AMS simulation [IRUN] where circuit with spice components is being driven by a stimulus code written in verliogams wreal.Here when circuit is fully operational my supply coming...
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