How to Compile System Verilog

Hi,

I use ncverilog: 05.70-s015: (c) Copyright 1995-2007 Cadence Design Systems, Inc.

TOOL:   ncverilog       05.70-s015:

and foll switches

    -update
    +access+r
    +sv31a

I egt the foll errs

class mem_base_object;
    |
ncvlog: *E,EXPMPA (../models/mem_base_object.sv,3|4): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
(`include file: ../models/mem_base_object.sv | line 3, `include file: ../models/memory_top.sv line 3, file: ../tb/memory_tb.sv line 4)

  mem_txgen txgen;
                |
ncvlog: *E,ILLPDL (../models/memory_top.sv,11|16): Mixing of ansi & non-ansi style port declaration is not legal.
(`include file: ../models/memory_top.sv line 11, file: ../tb/memory_tb.sv line 4)
  mem_scoreboard sb;

pls let me know a solution

Thanks

Chandra

Force10 Networks Inc, SJC