irun: design.v is verilog and verilog AMS

Hi,

We are migrating to an irun based flow to simplifiy our compile/elab/sim flow, and have a slight issue.

We have a file design.v, containing module design. Depending on a define, this can either be a standard digital module, or a WREAL model.

i.e. Within the file

`ifdef WREAL

wreal sig_name;

 `endif

This issue is that irun uses the file extesion to infer the type of file, in this case, it does not work.

This is a non-trivial design, so I have multiple verilog, vhdl and vams files, and using the -ams is probably not an option.

Question is: Can anyone suggest a solution? Is there an command line option that I missed, which applies to a single file only?

Thaks,

Steven