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Passing parameters form verilog to systemC
Hello, I want to call a systemC function in a Verilog shell using a wrapper, and I want to pass parameters from verilog to systemC, using "ncsc_get_param" in systemc side.But I have a problem, because...
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Whether DPI - C functions can be used in the environment where the top is in C.
I have created a simple example for dpi functions. Below is the code: CODE: C_file.c #include "stdio.h" #include "svdpi.h" //int main() //{ extern void export_func(void); void import_func() {...
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net connectivity at the top level using TCL
Hello,I would like to use ncsim's (or simvision's) shell to find out the connectivity of a net.For example, if I have a wire named clk in my top-level, I would like to get a list of ports that this...
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Problem when running simulation with Verilog-AMS and SystemVerilog together...
Hi, I am now working on a AMS verification using irun. I have an analog module (Verilog-AMS model, .vams) and a logic module (SystemVerilog RTL netlist, .sv) and want to integrate them together for...
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Envelop Following Analyses for Switching Amplifiers
Hi..,I want to do envelop following analyses in cadence for switching amplifiers, as tutorial contains the example in which linear amplifier is used and the same is not working perfectly with switching...
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I can't find "Part Manager" option in OrCad 16.3
Hy! Have you any idea, where is this "part manager" option from my OrCad 16.3? http://www.youtube.com/watch?v=AZRVEKfXfIcHere is my screenshot:...
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Viewing Verilog Tasks in Simvision
Hi,I have the following probe.tcl file included in my simulation:database -open waves -into waves.shm -defaultprobe -create -database waves -all -depth all -tasksrunexitIn the past I have been able to...
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Black boxing issue in IFV
I am facing problem while black boxing to end-IPs. The one IP contains signal which helps to start the system. So, I can't do black box to it. Still I want to check connectivity between those two IPs....
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ADE L Outputs Window does not work
The way I have always probed currents/voltages in ADE was to go to "Outputs>to be plotted>select on schematic" and click every node/pin I need. Now that I've moved to a new system this function...
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Bind SVA to VHDL Enumerated Type
Hi,I’m writing SystemVerilog assertions to check a VHDL state machine, and I need to bind the assertions to the VHDL component. What is unclear is how should I write the module port list? For example,...
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In UVM is there any Inheritance like "Specman e when Inheritance"..
Hi all,I need following Information,In Specman e: we are able to Create field inside the struct likesample Code: when WRITE'trans_type { addr: uint[31:0];}; when READ'trans_type { addr:...
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Functional Coverage Question
I have 2 coverpoints. Each coverpoint has auto generated bins as well as user-defined bins. In pseudo-code, I will describe them as follows: cp1: auto_bins, userdefined_bin0,...
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UVC Source Synchronous Interface
I am attempting to develop a UVC with a source synchronous interface. I need to be able to control the flow of clock and data to the DUT such that when requested, the clock and data are gated off...
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Breakpoints in simvision(Incisiv Simulator)
Hi, I started using simvision(Incisiv Simulator) in my project recently. I have set few breakpoints in few files. Is there a way to save the breakpoints that I have marked in this run, so that I can...
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How can I dump waveform using irun uder UVM environment
I downloaded an example (uvm_phases.tar ) from this websitehttp://www.testbench.in/UT_02_UVM_TESTBENCH.html I try to download the waveform with a tcl file database -open waves -shmprobe -create...
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Setting vhdl tb generic using irun command
Hi all,I've got a problem. In my tb I've got a generic: G_WAVEFORM_TYPE : string := "xxx" and i'd like to change "xxx" to "yyy" using irun "start.f" file, but i can't-mess -v93 -assert...
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increase virtual memory to sn_compile.sh
How do I increase the virtual memory allocated to sn_compile.sh? We have an environment compilation crashing because of an “out of virtual memory” error.
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How I can get test status from specman e at sv testbench
Hi, all!My UVM-SV testbench inncludes e vip. At the end of test specman prints status:Checking the test ...Checking is complete - 0 DUT errors, 0 DUT warnings. Can I get the number of DUT errors at...
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Capture project conversion
Hi all, I have a project (.OPJ & .DSN) made with Orcad 16.6, and I have an older release of Orcad (10.3). When I attempt to open the project within Orcad 10.3, The DSN file can't be loaded.Capture...
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