Clik here to view.
ICCR: toggle exclude for bits of a bus
Dear Sirs,could anyone give me an example on how to exclude a bit of an internal bus in the toggle exclude file for ncelab?For instance, if I useINSTANCE <pathname>:<bus_name>* I exclude...
View ArticleClik here to view.
net connectivity at the top level using TCL
Hello,I would like to use ncsim's (or simvision's) shell to find out the connectivity of a net.For example, if I have a wire named clk in my top-level, I would like to get a list of ports that this...
View ArticleClik here to view.
query on scope of events in e language
Hi My verification environment is in e language completely. I want to access the events of an unit from top level sequences i build. earlier i used to accesses the events anywhere in the seqeunces...
View ArticleClik here to view.
ADE L Outputs Window does not work
The way I have always probed currents/voltages in ADE was to go to "Outputs>to be plotted>select on schematic" and click every node/pin I need. Now that I've moved to a new system this function...
View ArticleClik here to view.
Promlem with markers
Hello, I have downloaded the lite version Orcad 16.6, and I have some problem with markers (voltage, current etc.). When I place marker on the circuit, the marker stays gray and no trace appears in the...
View ArticleClik here to view.
How to suppress the warning -- ASSERT/WARNING (time 277932200 PS) from...
We are using “irun” to run our testcase and we are getting the below warning. Due to this, we are getting a very huge log file (interms of GB). Please could you suggest why we are getting this...
View ArticleClik here to view.
Does irun 12.20 support multi-core simulation and how to do so
Does irun 12.20 support multi-core simulation and how to do so .I had ever use following "-processor" options. It seems that it does not work well. irun -processor 4irun -processor 4 -profthreadThe...
View ArticleClik here to view.
How to suppress these three mem_error/warning/abnormal transition messages
We are using “irun” to run our testcase and we are getting the below warning. Please could you suggest why we are getting this warning and how to suppress the same?. These assert/warning is related to...
View ArticleClik here to view.
vManager Failed: Unexpected error ( Out of memory )
When I run following command to collect coverage (There are 2000 vsof files)emanager -coverage -vsof " ./covwork/irun/*/*.vsof " &I got the Error: vManager Failed: Unexpected errorThe reason is...
View ArticleClik here to view.
INCISIV132/122 does not support some systemverilog 2012 coverage coding
INCISIV132/122 does not support following coverage code with error report: "ncvlog: *E, ECBECL… Range specification for a bin must start with (‘{’)" /// ------------- coding start -----------------bit...
View ArticleClik here to view.
Error while invoking Cadence IC615 virtuoso
HiI have installed Cadence IC615 in FEDORA 15. While invoking it by typing virtuoso, its giving folllowing error"ERROR: Can not find any 32 bits or 64 bits executable version of "virtuoso"" Can you...
View ArticleClik here to view.
Square Wave as input signal
How to give a square wave as input signal? There are various voltage sources like- VAC, VDC, VEXP, VPULSE, VPWL, VSFFM, VSIN, VSRC, etc.
View ArticleClik here to view.
Where can I get the equivalent circuit of device model?
Where can I get the equivalent circuit of device model? it is used in PSpiceAA. the model is one of aa_igbt library. It is more complicated than other IGBT model and it concludes more property name. I...
View ArticleClik here to view.
Hierarchical Coverage
Hi all, Can anybody guide me how can we do hierarchical access for covergroups.The following is the scenario. Module A has 4 covergroupsModule B has 4 covergroups I want to use A and B covergroups for...
View ArticleClik here to view.
Error : Overflow, divider cannot be zero
Hi All, I am using a vr ahb (eVC) and i get this error "Overflow, divider cannot be zero" . I have no clue how to debug this error. Coud anyone please throw some light on thsi error?
View ArticleClik here to view.
Mapping Libraries
I have a vhdl code that has the following lines: library ieee;use ieee.std_logic_1164.all library encode_8b10b;library decode_8b10b; The Cadence simulator is complaining about the encode_8b10b and...
View ArticleClik here to view.
coverage option weight
Hi , Can anybody explain me how "option.weight" used..if option.weight = 50 what happens and how it is going to effect the total coverage.if option.weight = 0 what happen and how it is going to effect...
View ArticleClik here to view.
case () inside gives errors with ncvlog
Hi, The following code gives an error with ncverilog. Can any one figure out why ? (version 12.2)case(ratio)inside[990:1010]: mon_txn.bit_rate_captured =3'b000;[390:410]: mon_txn.bit_rate_captured...
View ArticleClik here to view.
Uninitialized Clock Gate Cells
When simulating a netlist containing integrated clock gate cells (icg), we have many of these cells that propagate unknown states ('x') due to the fact that the clock signal is initialized high and the...
View ArticleClik here to view.
Color highlighting SimVision's console
All,is there any way to customize the syntax highlighting in SimVision's console.When I run UVM, messages and errors are automatically highlighed in different colors.I would like to syntax highlight my...
View Article