Problem when running simulation with Verilog-AMS and SystemVerilog together with irun

 Hi,

 I am now working on a AMS verification using irun. I have an analog module (Verilog-AMS model, .vams) and a logic module (SystemVerilog RTL netlist, .sv) and want to integrate them together for system verification, especially on the control of the analog module by the logic one. The testbench I am using is in .vams format. When I compiled it with irun, it gave the following error message and I don't know how to fix it. May I know if you have an idea on this issue? Thanks a lot in advance.

 ncvlog: *E,WOUPSR (/rtl/sv/dtcm_dsc_enc_ich.sv,293|27): A reference to an entire array is not permitted in this context [SystemVerilog].
(`include file: /rtl/sv/dtcm_dsc_enc_ich.sv line 372, file: all.sv line 121)
        history[i] = history_m[i];

Best Regards,

Solomon