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AMS Supply sensitivity in a text based testbench
 Hi i'm having an issue where i'm running a VerilogAMS testbench, which can instantiate verilogams blocks or their schematic equivalents. The verilogams models have supply sensitivity statements on the...
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Poor generation distribution results using count() method.
HiI am facing some problem using the count() method in list generation.I have summarized it to the test case shown in the next code: <'struct tc_s {   name   : string;   active : bool;   keep...
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Whats the difference between IES and IUS in cadence?
Hi All,I am new to Cadence simulator tools. Can someone please let me know the difference between the IUS(Incisive Unified Simulator) and IES(Incisive Enterprise Simulator)? Are there any difference in...
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Excluding Toggle coverage
Hi All,  I am doing coverage part for my subsytem . I am using "set_toggle_excludefile" in my .ccf at the time of Elab . I am using patterns , so it is excluding some signals which are covered .i want...
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Cadence taking time for initialization
Dear Team,I am running cadence in Ubuntu 12.04 32bit. While initialising/invoking any cadence GUI, it is taking relatively too much time(>10-20 sec). When it is running .cxt extention, it is taking...
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vr_ad register field printing
Hi,I am doing vr_ad register reading and writing operations and able to print the register name and whole register data but unable to print the every filed name under that register and corresponding...
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timescale mismatch
Hi,Does anybody know why the function in the code below is behaving differently when the input is a constant or a variable? It works for IUS8/20 but fails for incisive 12 or 13. Rafael -------...
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Autochecklist
 Hello experts,Need your help in figuring out how to fillin the checklist form that I created. I can't seem to find my way how to do it.Here's my scenario:I created a form where it contain a checkbox...
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initial statement issue in IFV
Dear Sir/Lady:I have a question while using IFV, there is a simulation model in my design, after running the verification flow for several cycles, I did not find PRINET was set to 1b'1, this seems to...
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probing all top mdules to a particular depth using $shm_probe
Hi, I have a testbench in which each test case adifferent assertion module. The assetion module is a top level in heirarchy(parellel to my test bench top which instantiates DUT). I need to dump the...
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merging three worklibs into one
we have a issue in merging 3 worklib( worklib_1,worklib_2,worklib_3 which has been created during compilation) during elaboration phase.Command used for creating those worklib is:(top file -...
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Code coverage exclusion case
Code coverage has added an "all-false" bin for Verilog case statements that do not contain a "default" clause. How to exclude a default statement in case statement in code coverage while we simulate...
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Why $random is not controlled by seed?
There is a segment of code below:for(int i=0;i<10;i++)begin$display("current random value: %0d", $random); endI use Cadence irun to compile and simulate this code. Although I add option " -seed...
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How to create coverage configuration file
 I want to run   "set_toggle_excludefile"  command . And I pass this command to coverage configuration file . And run that file in elaboration command but it did'nt run. where to create coverage...
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cadence ifv tool
what is the methodology underlying in IFV tool during design verification.i.e I mean whether BDD based or SAT based.If anyone knows please reply the answer or link of resource.Thanks in advance.Â
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Latest version of IFV
what is the latest version of IFV tool released from cadence? please reply soon. Thanks in Advance.
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CPF Simulations: Excluding PSL vunits
Hi,I have a PSL vunit attached to my top level module (via PROPDIR), and this vunit contains some signals to implement some simple modelling. The top level module is in a switchable power domain, and...
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Functional coverage of IFV tool
Can we check how much is the functional coverage of RTL design in Cadence -IFV tool  by using assertions  just like in test bench simulation and how to check the properties written for verification are...
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ncsim: *F,INTERR: INTERNAL ERROR
 Hi, Test : DRAM write and read up to 2GB .  Simulation fails with the following error. Can anbody please help me out?ncsim(64): 06.20-p001: (c) Copyright 1995-2007 Cadence Design Systems, Inc.ncsim:...
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NC: INTERNAL EXCEPTION
I got following informaiton, who can tell me why? Thansks.By the way, I'm using a uvm enviroment. ncelab: *F,INTERR: INTERNAL...
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