I'm trying to get a SystemC / Verilog simulation to run and am getting the following error messages:
There is no information on any of the warning or error codes in Cadence help or on this site. Has anyone got more information in these or suggestions on how to resolve them?
ncelab: *W,CUSRCH: Resolved design unit 'BLAH' at 'U_BLAH' to 'work.BLAH:v' through a global search of all libraries.
ncelab: *E,SCK109: complete binding failed: port is not bound to any interface: port 'tb.dut.signal_in' (sc_in)
In file: sc_port.cpp:247
In phase: end_of_elaboration.
ncelab: *E,SCK940: Error in SystemC elaboration
In file: sc_cosim.cpp:1249
In phase: end_of_elaboration.
ncelab: Memory Usage - 31.4M program + 72.5M data = 103.9M total (Peak 104.6M)
ncelab: CPU Usage - 0.1s system + 1.6s user = 1.6s total (2.2s, 74.7% cpu)
ncsc_run: *E,TBELABF: ncelab returned non-zero exit status
make: *** [comp_sc] Error 1