Hi,
I would like to pass some parameters to my e testbench at run time. Does Specman have the nifty feature of plusargs (what SystemVerilog simulators have). A similar feature would also be welcome.
Thanks,
Tudor
Hi,
I would like to pass some parameters to my e testbench at run time. Does Specman have the nifty feature of plusargs (what SystemVerilog simulators have). A similar feature would also be welcome.
Thanks,
Tudor