Communication between Verilog BFM and C-Based Verification bench

Hi

I have a SOC verification bench in C/ASM and integrated SV/Verilog based BFM/VIP. The system level tests are based on C/ASM.

To carry out functional simulations, the C/ASM tests are compiled, linked at the binary data of instructions are read into the On-Chip Memory for execution.

How can we enable the above environment where BFM(say its a master), waits for the system to reach to a point where system is ready and BFM(say its a master) can request data from/to the SOC?

To say in a short words, how can we achieve effective handshake between Verilog/SV(BFM) - C/ASM environments.

Could somebody please donate your ideas. 

Thanks
Arun