Xcelium simulator is not running when vhpi application is loaded.
I am able to load and execute a vhpi application that can read the vhdl hierarchy, and can put and get values.The problem I am having is that when I put a value on to. say an input, it does not...
View Articlepreprocessor directive
In e code one may use #ifdef <DEFINE_NAME> for preprocessor directive.if a given name is defined, it uses the attached code.Is there a syntax for: #ifdef <DEFINE_NAME> == TRUE?Thanks
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SimVision does not display a part of the signal plot
I am running AMS simulation for top-level verification and saving waves.shm database. I am plotting analog signals in SimVision for debug. However, at random some of the signals does not display some...
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fixed-point in simvision
Delta_ V1 delta_ V2 delta_ V3 are all 20 bit signals, but in my Verilog code, they are processed as signed fixed-point numbers, with 1 sign bit, 4 integer bits, and 15 decimal bits. So he is actually a...
View ArticleWhen running upf simulation power net is stuck at 0
I have the following upf constructs:create_power_domain PD_TOP \ -include_scopecreate_power_domain PD_V1P8_AVDD \ -elements { A/B }create_supply_port NET_V1P8_AVDD \ -direction...
View ArticleStuck at a package not bound error in the accelerated UVM course
I have been doing the Cadence Accelerated UVM with UVM 1.1 course and I am stuck at the part where you connect your testbench to the DUT. I keep getting a package not bound error even though I have...
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change text editor colors (not trace colors) used in Probe
I want to change text editor colors (not trace colors) used in Probe when viewing the simulation OUTput file. See below, I can't seem to create a narrow enough search criteria to find any info on this...
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simvision failed to load the svwf waveform file "Error: bad condition name...
After loading the svwf file saved before, the waveform window did not display any waveform, and an error with bad condition name was reported in the console window. What was the reason for this and how...
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simvision waveform window "placeholder for future object creation"
After loading the previously saved svwf file, there will be a horizontal line above the waveform appearing in the waveform window, and the reminder "placeholder for future object creation". Why is this...
View ArticleERROR(ORCIS-6238): Part_Number property type was not configured correctly in...
I used the access database and successfully added the library, but there was an error during the addition process. I tried adding the library from the official website, but it still didn't work. The...
View Article$display() is executed immediately after simulation start although the...
Hello!I'm testing a small design of my own and I stumbled upon something I can't understand. When I hit 'run', I see immediately "Hello!" printed. Here is part of my testmodule:initial begin...
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verification metrics on IMC
Hi,I'm using IMC tool and I'm trying to understand what is the difference between Types and Instances in the added figure. The figure is an html output of IMC tool.Some time I see the same modules both...
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The circuit is not giving correct plot for output
Dear All,I am a beginner in Cadence and I am creating this differential amplifier to see typical Vx-Vy output. But the plot is very wrong I believe or it is not matching the one we see in books. Please...
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how to force the variables inside a class? i'm facing this error "FOAUTO"
My intention is to force variables inside a class of type uvm_component. But as I cannot show that confidential code, i'm trying to replicate a similar code.Here i'm able to force the variable j inside...
View ArticleTagging uvm_errors in waveform file for post-processing
Hi,Do anyone know if it's possible in simvision waveform viewer to see a timestamp of where uvm_errors/$errors occurred in a simulation via post-processing? Cheers,Antonio
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incorrect output of multiplication in jaspergold
I want to use jaspergold to formally verify functionality of my custom multiplier. I am computing the expected result using A*B to check against output of my multiplier. Here, A and B are two logic...
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ERROR - Noise Analysis
Hello, I want to simulate my circuit using the Noise Analysis.I am trying to use V(Out+)+V(Out-) as Ouput Voltage.But I am getting following error:*Analysis directives: .AC DEC 1000 1 100k.NOISE...
View ArticleHow to invoke the Xcelium Design Browser from Command Line?
Hello,How to invoke the Xcelium Design Browser from Command Line? As for browsing the TRN (signals recording) file, the SimVision is used.What tool is used to browse the simulated design (hierarchies...
View ArticleJasper's elaborate -bbox_i seems to have no effect
I'm trying to use Jasper for checking parameter propagation in a large design. I have a list of top-level parameters, each with a HDL path of a module parameter somewhere lower in the hierarchy that's...
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UVM Adapter for Pipelined protocols like AHB, AXI etc
Hello,I have been running this `uvm_reg_hw_reset_seq` sequence for the AHB protocol. My UVM Adapter looks like:Issue: When I use basic reg.write, my write access are working well, as that is managed by...
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