My intention is to force variables inside a class of type uvm_component. But as I cannot show that confidential code, i'm trying to replicate a similar code.
Here i'm able to force the variable j inside the module main but unable to do a force on the variable num which is inside class example.
i tried to change the scope, but the simulator always throws "*E,FOAUTO: Invalid way of setting automatic variable:"
what is a valid way to force the variables inside the class. I've read the document on the force, but it mentions about verilog/vhdl objects.
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