Using Xcelium, xrun -nogui option, where are the simulation results
I'm completely new to Cadence. I've been able to run a very simple simulation with the -gui option. Simvision opens, I add the variables to the waveform viewer, and press run. All is good.I don't...
View ArticlevManager import from ODF does not update vplan
I opened a vplan in vManager and exported it to an ODF file. Then I edited the ODF file and modified some attributes.Then I imported the ODF file to vManager and the vplan was expected to be...
View ArticleImporting ODF to vManager does not update vplan
I exported vplan to .odf file in vManager and after editing it I imported it to vManager. The vplan was expected to be synchronized and updated. However, nothing has changed to it. Does anyone know why?
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How to use the navigation keys in tcl debugger?
xrun -tcl <file_name.sv>The above command should compile, elaborate, and stop simulation at 0 in command line mode.At this point we can setup the breakpoints and perform other features of...
View ArticleUVM debugging: How to save and load signals during an interactive session in...
Hello,I am aware of command script .svcf file that saves signals and loads them in while opening Simvision.I am wondering, if there is a way for saving signals while we are in an interactive session...
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Using Vmanager Pre-Script to launch a timed script
I would like to send an update about a vmanager regression status x days after the regression has been run. In the current environment, the vmanager regression is creating a new filepath for logs...
View ArticlevManager crashes when analyzing multiple sessions simultaneously with a fatal...
When analyzing multiple sessions simultaneously Verisium Manager crashed and reported below error messages:# A fatal error has been detected by the Java Runtime Environment: # # SIGSEGV (0xb) at...
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explain/correct my understanding between average/covered in imc metrics
I'm working on the code coverage. Doing a metrics analysis by default we see overall average grade and overall covered. But when i do a block analysis on an instance i see overall covered grade, code...
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View ArticlePermission issue on xceilum
The AMS simulations on Cadence Virtuoso works fine without any permission issue. But when I netlist the AMS Configuration for running along with UVM and run simulations, I face “permission denied on...
View ArticleNot able to Invoke XRUN
Hi,I had installed XCELIUM in my personal computer, license manager is installed in my college server. i have set all the paths and env variables for using this tool but when i invoke xrun command its...
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Parameterizing an Instance
Hi,I want to parameterized width and length of a NMOS, but it ignore it and I face this error:*WARNING* Value input must be a number - setting back to previous value.Does anybody know how I can fix...
View ArticleHow do I create a basic connectivity csv?
First time user of JasperGold. Chip level verif. I want to prove that an arbiter and a buffer are connected.I see, from the user guid, that I should provide a connectivity map, but i have no idea how...
View Article[Xcelium][xrun] Simulate with multiple builds
I want to do a 2-step build->simulate as follow:1. Make multiple builds using xrun -elaborate [other options]. The purpose is to create multiple builds with different compile-time macros...
View ArticleLVS netlist
How could we inherit parameters from schematic to a layout netlist?Those parameters are user defined parameter given in CDF and netlsiting in schematic.
View Articlexcelium - CSI: *F,INTERR: INTERNAL EXCEPTION
I just completed the setup of xcelium and I am trying to test a very simple vhdl file - I got " CSI: *F,INTERR: INTERNAL EXCEPTION" without any further explanation. Could someone point me to how to...
View Article"How to disable toggle coverage of unused logic"
I'm currently work in coverage analysis. In my design certain register bits remain unused, which could potentially lower toggle coverage. Specifically, I'd like to know how to disable coverage for...
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Real Number Modeling Streamlines Mixed-Signal Verification
Semiconductor design is swiftly evolving, with mixed-signal design playing a pivotal role. This approach seamlessly integrates analog and digital circuits onto a single SoC, offering notable...
View ArticleWhen running upf simulation power net is stuck at 0
I have the following upf constructs:create_power_domain PD_TOP \ -include_scopecreate_power_domain PD_V1P8_AVDD \ -elements { A/B }create_supply_port NET_V1P8_AVDD \ -direction...
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