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Instantiate SystemC module in SystemVerilog module with real/double ports
I would like to instantiate a SystemC module inside a SystemVerilog module with real/double ports.Here is some source code:// file model.h:#include "systemc.h"class model : public sc_module {public:...
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SystemVerilog EEnet input driven by current source
Hi,I am using the Cadence System Verilog EEnet package to model analog ports.I am running the simulation in the Virtuoso (6.1.8) environment. I do have a problem with input ports defined as EEnet and...
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vAPI filter return no duplciate
Hi all,I want to get the list of ran vsif from the vAPI.For this I use the following request with following filter : - POST : https://serverName/vmgr/vapi/rest/sessions/list - filter :...
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fatal voltage source/inductor loop
Hi, I am modeling PLL in verilogA. It gives an error that there is fatal voltage source/inductor loop. I wonder what this error means? and how it can be fixed?Thanks,
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Xcelium: Altering return value of $temperature in digital simulation
We would like to use the $temperature function in a SystemVerilog behavioral model in digital simulaion using Xcelium.By default the $temperature function returns 300.15 degree Kelvin in digital...
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VManager + DRM user specific config (HTCondor)
Hello Everyone,I am in the process of setting up a VManager + HTC server farm (using HTCondor) for regressions.As HTCondor is not natively supported by Cadence like NC or SGE is, I need to specify it...
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Prevent SimVision Schematic Viewer from Re-Zooming/Centering after tracing a...
Hi, I think I have a simple request, but cannot seem to find the right option.SimVision preferences have this option for the schematic tracer. Lets say I have a module port and wish to trace that...
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The Best Way to Learn SystemVerilog Accelerated Verification with UVM –...
Hi Everyone,UVM is a heavily used, standard, proven, easy-to-use, automated verification methodology in our current industry. With the growing use of UVM methodology, engineers need to have an in-depth...
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Conformal Litmus vs JasperGold CDC
Hi, What is the CDC tool from Cadence ? It looks like there are at least 2 choices when googling the internet. 1. What are the difference between Conformal Litmus vs JasperGold CDC ?2. Does Incisive...
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When to ideally run an UNR Analysis?
Cadence recommend running the UNR analysis when your code coverage metrics are near 70-95% depending on the size of the design.RTL and code coverage data are inputs to the formal tool for UNR analysis....
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How do I update a 'test case' attribute in a vPlan using the vManager API (vAPI)
Hi All,I have a vPlan (in .vplanx format) which contains a hierarchy of sections and at the bottom of the hierarchy, each section contains a test case, checker or coverage item.Each item has associated...
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Model simple inductor in SystemVerilog using EEnet
I have a simple SV capacitor model using EEnet as shown below. This simulates with no issues when driven by 1V square wave as shown below:`timescale 1ns/1psimport EE_pkg::*;module CapGeq ( P );inout...
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Find the test which hit a specific coverage attribute
I would like to know if there an option in vManager using TCL to find the test which hit a specific coverage attribute (Expression/Toggle/FSM). We have 1000s of tests and it would be easy if I can find...
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xmvlog: *E,NOPBIND (../src/soc_tb_top.sv,46|20): Package soc_test_pkg could...
file: soc_tb_top.sv`include "soc_if.sv"module soc_tb_top; import uvm_pkg::*; import soc_test_pkg::*;....endmoduleHere is my Makefile: xrun -uvmhome $(UVM_LIB_PATH) -uvm -64BIT +incdir+../src...
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xmvlog: *E,NOPBIND (../src/soc_tb_top.sv,46|20): Package soc_test_pkg could...
file: soc_tb_top.sv`include "soc_if.sv"module soc_tb_top; import uvm_pkg::*; import soc_test_pkg::*;....endmoduleHere is my Makefile: xrun -uvmhome $(UVM_LIB_PATH) -uvm -64BIT +incdir+../src...
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Irun with UVM and vams file
Hi, I have a generated netlist for an analog mixed-signal design, I have the netlist.vams file and I have a UVM environment how can I run the UVM test case using irun ?
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Save a view using batch-mode commands of vmanager
My requirement is that I have to select different attributes for sessions/runs and after the attributes are selected, the view has to be saved. I know how to do this in GUI mode, but I need to know how...
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Formal Verification Approach for I2C Slave
Hello,I am new in formal verification and I have a concept question about how to verify an I2C Slave block.I think the response should be valid for any serial interface which needs to receive...
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Troubleshooting JasperGold error EFSV032 regarding conflicting inferred...
I am using the JasperGold FSV app to identify safe faults in a Verilog design. I am applying SystemVerilog assumptions in the verification task to represent application-derived constraints.Sometimes...
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vManager vAPI authentication
Hello Support Team,I have issues trying to use the vAPI, as it show an error that requires full authentication: <h2>HTTP ERROR 401</h2> <p>Problem accessing...
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