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NCLaunch VHDL compiler *F,DLUNNE error
I'm trying to compile a VHDL code via NCLaunch. However, I keep getting the following error on the console*F,DLUNNE: Can't find STANDARD at /vlsi/apps/cadence/ius/8.2HF015/tools/inca/files/STD.There...
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Post synthesis simulation with XCELIUM - SDF
hi,due to technical problem i am running simulation through terminal. Therefore, I have a Verilog file, a test bench and i have also exported from Genus synthesized netlist and sdf file. Now, how can i...
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Unable to Import .v files with `define using "Cadence Verilog In" tool
Hello,I am trying to import multiple verilog modules defined in a single file with "`define" directive in the top using Verilog In. The code below is an example of what my file contains.When I use the...
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Export a Breakpoint
Hi all,I was running a simulation with Xcelium in Simvision and I save few breakpoints.I would like now to run another simulation (so from a different console) and loading one of the breakpoints of...
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How to get product to license feature mapping information?
When I run simulation with irun, it may use may license features. How can I know which feature(s) a product use? I get below message in...
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Failed to inject fault at (ncsim)
Hi,I'm doing fault injection with ncsim and got stuck at the following (and not so useful) message: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174." I already tried with other...
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[IMC] Toggle coverage report
Hi,Is it possible to consider only 0->1 or 1->0 transition condition in toggle coverage report ?I mean that I want to consider that a net is full covered if one of this transition is respected...
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ncsim: *E,FLTIGF: [FLT] Failed to inject fault at NET
Hi,I'm doing the "The Targeted Fault Campaign" with ncsim and got stuck at the following message: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174." I already tried with other...
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Portable Stmulus tool Perspec System Verifier
Hi all,I would please like to know if the Cadence tool for Portable Stimulus Standard namely Perspec System Verifier has an academic trial version. If not, the website says one can request a demo. But...
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VManager : Increase and Decrease the number of parallel runs in the on-going...
While firing a regression that might span multiple working days, We need to increase and decrease the number of parallel runs to distribute license usages.During working day hours, we would like to...
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Add a button to specview?
I remember from long time ago, that there was some way of adding buttons to specview. I see a global sn_display object, that seems to have some API that might be used for things like that, but can't...
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Can Cadence Incisive Enterprise Verifier be used for functional verification?
I understand that Cadence Incisive Enterprise Verifier is for Assertion Based Verification, it has within it Incisive Enterprise Simulator which lets the tool generate testbench stimulus from...
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How do we extract a full path design from Scoreboard when there is a `uvm_error?
Hi,How do we extract a full path design from Scoreboard when there is a `uvm_error?For example,my_module has the following assigments: (array of virtual interfaces, while each VF accepts data and...
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Excluding unused functions in JasperGold Superlint
Hi,Is there a way to avoid getting lint warnings from unused functions in JasperGold Superlint?If I import a shared package that contains a function with linting errors, I don't want to see errors for...
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Lint errors
Jasper SuperLint mesage pops to change the input of the top level module to register and register the input signals to increase controllability. how to resolve it
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Does driver trace through system verilog interfaces ever work?
Interfaces are great but it is so frustrating that driver tracing through them never works in Simvision. Does this work for anybody or is it universally broken in Cadence simulators?
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generate over a loop the same module with different parameter and maintain it...
Hi,I've encountered in an issue that I'm trying to generate an interface with different parameter (DW) over a loop.Therfore, I found that I've two problems;1. How to generate the block (interface in my...
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[JasperGold] Behavioral Analysis - How to exercise it properly?
Hi,I'm running behavioral analysis in the apps RTL Development and Executable Specification from JasperGold, but the only results i obtained were:Recipe Trace Lenght (old and new): N/A.Assertion...
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Analog circuit designing
Why do we require high voltage swing at the output of line drivers?
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e code coverage
Is there some support for getting code coverage of my e files? I'm working in an environment where I suspect a lot of dead-code.Thanks,Avidan
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