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OSVVM Support and Xcelium
Hi everyone,It is my understanding that OSVVM release 2018.4 is pre-packaged with Cadence Xcelium version 20.03. Are there plans for newer/latest release(s) of OSVVM will be pre-packaged with Xcelium?...
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Functional Coverage using IMC
Hello All I have three test cases, say test_1, test_2, and test_3. I have generated functional coverage for each test case individually. when I try to merge the coverage of test_1, test_2, and...
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Tool to generate UVM RAL Model
Hello All, I want to generate the UVM RAL Model from ".xml file" or ".csv file". what is the tool used for it and Procedure to generate RAL Model.!
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Array Usage Initialization
Hi All,In the following code, 2nd element is 'h10A0, it must PASS, but it is failing, may I know the reason ?module typedef_ex; bit [2:0] addr [15:0]; bit [2:0] data [7:0]; initial begin...
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Randomization Failure from TB
Hi All,In the UVM environment, received "The randomize method call failed, the unique ID of the randomize is xx."I am driving one command and followed by two address from TB side, like; CMD ->...
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Hướng dẫn cách chơi Rồng Hổ Online hấp dẫn tại FB88
Rồng Hổ Online là trò chơi hàng đầu được phần lớn người chơi tại các nhà cái tham gia chơi cá cược. Với luật chơi đơn thuần, Rồng Hổ thích hợp với rất nhiều người chơi; từ người mới tham dự casino...
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Instantiate SystemC module in SystemVerilog module with real/double ports
I would like to instantiate a SystemC module inside a SystemVerilog module with real/double ports.Here is some source code:// file model.h:#include "systemc.h"class model : public sc_module {public:...
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vManager Regressions failing due to Exclusive Lock
Hello Everyone,We have had some issues with some regressions running with DRM setup and vManager due to an exclusive lock error.This makes the whole regression get stuck on waiting, completely breaking...
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signal transmission problems of CDC check
Hi: Reg 2 has two clocks available, which one is used is determined by the a signal.I want to do a cross-clock domain path analysis from reg 1 to reg 2 When reg 2 uses clk 1，and use “check_cdc...
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Vmanager and the logs tab page
Hello,I am trying to find out if it is possible to modify the files opened in the logs tab.Indeed I want to add a file that is generated by a script, how can I proceed?Thanks you
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IMC Question : Multiple Coverage Entities
Hi,I am observing in IMC that certain assertions are shown with attribute of "MIX" in red -> multiple coverage entitiesWhat is the meaning of multiple coverage entities attribute in IMC for a...
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Cross coverage of two covergroups
Hello All I want to cross-coverage between two different covergroup, Is it possible to do this? Does the Cadence tool have this feature?`
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ROM design
I am trying to write verilog code to store 2^36 outputs of C432 benchmark circuit in ROM. It is taking more than 3 days to write all the address, still I haven't completed the code. Can you please...
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Is there a way to view what line of HDL code is being executed at the moment...
I'm trying to run a behavioral simulation of my Verilog design, but somehow the Xmsim simulator seems to go into an infinite loop and the simulation stops advancing. It literally gets stuck. I was...
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getting xrun to quit on error during simulation
We have a need for xrun to exit during the simulation step of our system verilog design when an error occurs. The error we want to exit on is generally from an assertion (*E,ASRTST) but also could be...
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black box in the lec cause the mismatch
I use the module from Synopsys in my own module, and those modules become BlackBox dring the lec and cause the not-mapped points. Can anyone tell me how to solve this?
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IEEE float radix in Simvision
I want to view some signals in floating-point format in the waveform window. I can easily change the radix to hex, decimal, binary or octal; but there is no option to change to float. How can I achieve...
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Prevent SimVision Schematic Viewer from Re-Zooming/Centering after tracing a...
SimVision preferences have this option for the schematic tracer. Lets say I have a module port and wish to trace that step by step (using double clicks). For small modules this works fine, but once...
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JasperGold SAT solver capacity
I use JasperGold SPV app and the warning message show that 'SAT solver RegionAllocator max capacity'Is there any command can set the max capacity of SAT solver? Thanks!
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license search order in Xcelium
Our company used to have licenses for both Xcelium_Limited_Single_Core and Xcelium_Single_Core. Recently the management decided to only buy the last one. Now, when somebody tries to run xmverilog, it...
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