file: soc_tb_top.sv
`include "soc_if.sv"
module soc_tb_top;
import uvm_pkg::*;
import soc_test_pkg::*;
....
endmodule
Here is my Makefile:
xrun -uvmhome $(UVM_LIB_PATH) -uvm -64BIT +incdir+../src +incdir+../sim +incdir+../tests ../src/soc_tb_top.sv -seed $(SEED) -access +rwc ../src/soc_tb_top.sv
Here is my soc_test_pkg.sv
package soc_test_pkg;
import uvm_pkg::*;
import soc_env_pkg::*;
`include "uvm_macros.svh"
`include "soc_base_test.sv"
`include "soc_jesd_csr_test.sv"
endpackage
This compilation error shouldn't happened. This is very straight forward testbench flow. Please help as I have been debugging for 3 days now.