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Sleep transistor for leakage reduction
Hi all,Anyone has experience working with sleep transistor simulations?How do I go about measuring the delay of the circuit if I'm activating the sleep transistor? Since the output should not be...
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Enable recording from the sequence
Hi, I'm trying to record sequence_item from the sequence using the following code;task body(); repeat(10) begin wait_for_grant(); frame = norm_seq_item::type_id::create("frame"); begin_tr(50);//50 is...
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Functional Coverage with irun command
Hi, I trying to generate functional coverage using irun command.I have given "-coverage functional" in the elab phase. I am not getting any of the data orirnted coverage. Can anybody knows what I am...
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Can't find package sqlite3 in virtuoso
Hi!, I'm not sure if this post should be in this category.I would like to ask help in my problem as follows: We have installed a tcl in /usr/local/lib.Using virtuoso, we have encountered the problem...
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vr_ad reset check
Hi all, When we define as vr_ad reg_fld for each reg_file we used to provide the reset value of each field. As i know the application for this is when we call reset() function for that reg_file it will...
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Need help in assertion based connectivity checking
Hi,I am new to the formal verification process and I am trying to use it for verifying the connectivity between some modules in a SoC. I am using Incisive Formal SoC Connectivity Solution (V2.01)...
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Verification of concurrent modules with IFV
Hi guys, This is my first post. So, I hope I'm writting it in the correct place. I need a help to verify two concurrent modules (A and B) instantiated in a top module (Top). The concurrent modules...
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ncsim: *E,UNKMOD: unrecognized modifier for the coverage -code command...
I encountered this error when I was trying to collect the code coverage of my design. The nc simulation command line contains" +ncinput+./testbench/sim/ict.tcl". And the contents of the file ict.tcl...
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irun: Simulating an already generated snap-shot.
Hi, I want to generate a snap-shot with name house and simulate it later.To generate snap-shot, I use the following command, irun -elaborate -snapshot house source.svThis results in a folder...
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Re: Simulating an already generated snap-shot.
Try just 'irun -r house' without the library and view name. You could also use 'irun -R' which will pick up the last snapshot created.Finally. make sure that if you used 64bit for elaborate, that you...
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Tracking regression results with an SQLITE database
Hi , I would like to keep track of the verification status of my project (verilog/systemverilog) coverage and pass/fail status of tests during the life of the project. Ideally I want to create an...
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How to overcome DC convergence error in ultrasim?
Hai, I am using ultrasim to simulate the circuits. I always get the DC convergence error while simulating and the ultrasim simulation fails. This happens even for simple basic gates and also for other...
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IFV assertion check problem
When I was running a IFV assertion check,the result was "Pass",but the trigger item showed "Blank",and the Trace item showed "Not run". I want to know that whether the assertion check was OK or...
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Reg:Coverage improvement
Hi StephenH, Thanks for your reply. Please help me to sort out this issue. Ex: If There are a.v,b.v & c.v files in one Top_module.v then the coverage will be around 80%. To improve the...
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Additional TCL Documentation?
I'm having trouble learning about the TCL API, despite having read the Extensions application note in some detail. I've done quite a bit of programming (C, C++, Java, COBOL, x86 assembly, bash, etc) so...
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How to read the Stream Counts in irun 10.2 profiler
Hello!I am doing a RTL simulation and running the profiler with irun 10.2.In regards to the lines where I have added xxx's to the right- Where can I find information on what these mean ?- is there...
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Is there any option like +ntb_random_seed in VCS for ncverilog?
I wonder how to generate random seed for simulation with ncverilog. Is there any option like +ntb_random_seed_automatic? Thanks!!
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UVM_REG:: How can we use multiple bfm drivers to same regmap using uvm registers
We have to use multiple bfm driver to regmap and at same times we don't want to change UVM API's for example: uvm_write uvm_read But I see that in connect stage regmap default sequencer is set to one...
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SystemC module array of ports binding with Verilog module
Hi, I am integrating SystemC module with SystemVerilog verification environment. One of the SystemC module has an array of sc_in and sc_out ports, for which I am creating a Verilog wrapper with...
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IMC Exclusion Problem
Hey all, I am using IMC for my coverage .The problem is the tool automaticaly excludes some block coverage or expressions from the coverage.It shows "Exclusion Rule type : simulation time".Can someone...
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