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Spectre suddenly stops running during Parametric Analysis (ADE L)
Hopefully somebody can answer this question but, we are having trouble trying to get a Parametric Analysis to COMPLETE when running ADE simulation. Every time we run it, spectre seems to stop running...
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Promote SVA failure to uvm_error
How could the System Verilog Assertion failures be promoted to UVM_ERROR to be reported by the UVM environment?I am aware that it can be coded as:assertion_name:assertproperty(//...
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Capturing glitches in Xcelium
Hello,So I am seeing this weird behavior in my simulation where a register captures a value but nothing in the input logic cone has changed.For e.g., a <= (b & c) | (!d) | (~e &f)where a is...
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same value for a RANDC variable of base class in extended class objects
i have a randc variable "index" in c_base. i've two new classes (class_1 & class_2) extended from base_class. when randomizing the extended class objects, i observed the variable "index" is having...
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NCELAB WOUPSR errors
I have a UVM testbench which gives the following errors when I compile:$cast(arg, tr); // Need run-time casting because at compile time T1 can be scalar. |ncelab: *E,WOUPSR...
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VPI : vpiLoad iterator on vpiIntVar
According to the IEEE Std 1800-2012, VPI code should be able to determine the variable loads of a vpiIntVar or vpiIntegerVar using the vpiLoad relationship iterator. The relevant section is 37.17 of...
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How can I implement a sequential coverage?
I have an event nameddtx_intrpt_e. I want to create the following coverage: On tx_intrpt_e wait few cycles cross uarttx_dma_sreq==1.Where uarttx_dma_sreq is a port of the interface.p.s"few cycles"...
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How to disable deferred assertion error message dynamically?
Hi,I've a deferred assertion enabled by default. For example,sequence a_seq; (A) ##1 (A)[*100];endsequenceproperty a_ast;@(posedge clk)1 -> a_seq;endpropertyAt times I need to terminate the...
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Indago tcl commands
Hi,Anyone knows where I can find tcl commands supported by Indago debug analyzer app
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Coverage not getting hit when trying with IUS simulator
HiI am seeing discrepancy in cover bins getting hit , I have total 10 cover bins out of which valid 8 get hit with VCS , however with IUS none of my valid bin gets hit.I have put display prints to see...
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PSpice A/D Stuck in lite version even if I have a license dongle. How to...
I have check lmtools and the license server is functional with the dongle. OrCAD Capture says that it is full versionRunning simulation from there brings up PSpice A/D lite version instead of a...
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How to read label inside a particular instance and check its connectivity...
Hi,I have multiple instance in top cellEach instance has some labels inside it.How I can get the instance name and read the labels inside it, and check to which label(of another instance) it is...
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Can we create directories using the code we write in Ocean script?
I am trying to develop a code in ocean script which can automatically create folders during the runtime to store my results. But, I am not able to create any directories using my '.ocn' files, is there...
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How to query if a database has been opened in Simvision with tcl command?
For example, in tcl console, we can rundatabase open nc_wavesto open a database, but how if I want to achieve the following in tcl console,1) check if there's an existing opened database;2) if yes,...
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Specman - init a param value of internal sequence (execute from another...
I have a sequence (e.g SANITY_TEST seq) which execute another sequence (e.g BOOT seq). The BOOT seq contains the following param:index_v : uint(bits:4) ;I have the following test : extend MAIN...
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Constraints for multidimensional array
Hello guys. Have no idea why my code doesn't work in IUS 15.2/051 simulator. I tried to generate two-dimensional array with random size , but randomization method was failed ?! Can you make a comment...
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How to remove multiple Markers quickly in Simvision?
Hi,I have set lots of Markers in Simvision to debug waveform, but the Markers will be kept even if I open another database.Is there any way to remove those markers quickly?Thanks.
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Interface port coercion
Hi,I recently came across this two papers which would fit really well in our block and system level testbenches:Verification prowess with uvm harnessUVM HarnessThe idea is to declare all interface...
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ERROR: ncvlog: *E,EXPRLC (/file/hierarchy/**.sv,14|18): expecting a left...
I see the following compilation Error, when I am trying to build/compile the following code. I don't see any issue in the below code, Can anyone please help me to figure out the issue.I have a function...
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How to get the output from this button in Simvison(counts of edge, high/low...
Hi,I'd like to write a batch commands to count the edges/high time/low time for some signals by tcl command. By now I know the Simvision offers a button to achieve this for one signal.Is there a tcl...
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