Hi,
I recently came across this two papers which would fit really well in our block and system level testbenches:
Verification prowess with uvm harness
The idea is to declare all interface ports as inputs and, if anywhere in the testbench a certain port is driven to a value then the port is "coerced to inout" at compile time.
This feature is part of the SystemVerilog standard:
23.3.3.1 Port coercion
A port that is declared as input (output) but used as an output (input) or inout may be coerced to inout. If not
coerced to inout, a warning shall be issued.
It is a really interesting feature and become even more powerful when coupled with the bind statement.
However, when trying to compile some example code with irun I get this error:
A net is not a legal lvalue in this context [9.3.1(IEEE)]
So, it seems that irun doesn't support it (tried the same example code and it runs fine on other simulators).
Has anyone come across this issue before? Is there any magic switch that would enable it?
Regards
Mario.