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Replace "`includes" with in-line modules - NC-Verilog
Hi,I am using the Virtuoso Verilog Enviroment (NC-Verilog), in order to generate the functional Verilog model of my top Schematic. For some of the components of my Schematic, I have written their...
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NC-Verilog user manual
Hi,I am not able to trace the user manual of NC-Verilog. I need it, because I am trying to solve this issue:...
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Is there a way to change the value of a voltage source (or a generic...
Hello all, I was wondering if there is a way to change the value of a voltage source interactively, during the execution of an AMS simulation. In SimVision, I can not deposit a value on a VerilogA...
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xrun timing check
Hi,I have to perform an RTL simulation using some library cells and some models. Both files have the timing information through specify/specparam definition.I would like to suppress timing information...
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PSpice A/D Stuck in lite version even if I have a license dongle. How to...
I have check lmtools and the license server is functional with the dongle. OrCAD Capture says that it is full versionRunning simulation from there brings up PSpice A/D lite version instead of a...
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How to read label inside a particular instance and check its connectivity...
Hi,I have multiple instance in top cellEach instance has some labels inside it.How I can get the instance name and read the labels inside it, and check to which label(of another instance) it is...
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What is the recommended usage : vaelab vs hdlSynthesize?
Hi,I am going through palladium uxe userguide, which gives user two option to do an rtl/hdl import in ICE mode. User can use either1) vavlog+vaelab utilitiesor2) hdlImport+hdlSynthesize xel commands...
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Where can I ask tools question on Synopsys VCS simulator?
I mainly used Cadence and it's the best simulator tool out there I know. But I have to do IP support to a customer using VCS. The tool is really too complex for me to get done some of the most common...
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AMS Netlister Error: "Illegal non-local reference to constant function...
I am simulating corners using ADE XL and the AMS simulator. Netlisting fails with the above error. The offending line in the netlist is: defparam I15.CORNER = pPar("CORNERVAL");I15 is a...
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parametrized cover class instance mapping in vplan
I am using parametrized cover class and I am mapping instance of these cover class with vids defined in vplan.But every time when I am changing the parameter(sccr_clk_cov#(16,...
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Fork a task with parameter from within a function
Hi,Below is what I've tried to start a task with parameter from a function. function fork_task_in_func() for (int i = O; i < 3; i++) begin fork print_me(i); join_none end endfunction task...
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How to show connections for a wire?
HI,For a given wire, I'd like to find the signals connected using that wire. Is there any way to fulfill that? It's better to use some tcl command to automatically show connections for a bunch of...
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SDF back annotation in systemVerilog design using interfaces
I have a DUT which is encrypted netlist and .sdf file (normally we do functional and timing simulations with these inputs). I used interface feature in SystemVerilog so I don't define any port for the...
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How to show posedges by Simvision expression?
Hi,In Simvision, users can easily view conditional combination of some signals by its expression feature.However, if I want to view conditions like,@posedge(A) & (B == 'h1234)How can I achieve this...
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DLCSMD Errors
Hi,I'm getting the following compile error:xmvlog: *E,DLCSMD: Dependent checksum verilog_package work.foo_pkg:sv (VST) doesn't match with the checksum that's in the header of: verilog_package...
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What could be the reason of *E,DLCSMD error?
Hi,I ran into an error like,*E,DLCSMD Dependent checksum module A.B:module (VST) doesn't match with the checksum that's in the header of: snapshot worklib.top_dut:sv (SSS).*F, NOSIMU: Errors...
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What's the definition and the function of value()
Hi, allI'm new to specman E, and begin learning it by reading Design Verification with E. I've many times the utilization of function value, such as:keep tx_monitor.file_logger.to_file ==...
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Puzzled by definition of this struct
Hi, allme again, I've read a definition of struct as follows:-- Definition of the packet struct struct packet { kind : [good,bad]; addr : uint (bits : 2) ; len : uint (bits : 6) ; data [len] : list of...
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How do I exclude my CPU netlist from probe?
Hi all, I use the following statement to probe all the hierarchy in my testbench. However I wish to exclude the CPU netlist model in tb.design.hier2.CPU_netlist. How do I do that? "database -open...
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black-boxing using "-bbox" in Jasper
Hi,In Japser there is a provision for black-boxing., What is the difference between:a. black-boxing during compile/analyze b. black-boxing during elaboration.-Thanks
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