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Where does irun search for source files to generate implicit libraries?
From the ncvlog.log I seeUsing implicit TMP libraries; associated with library worklibGenerating native compiled code:... ...thereafter a library directory named inca.<my_lib> was built under the...
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Simvision doesn't always save waveform formatting
Hello, I'm running into a very frustrating issue/bug w/ the waveform viewer in Simvision where the waveform display formatting is not always saved to the svcf file when the "save command script"...
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SV: How to name an unnamed block
If I create a variable in a for-loop: for(int i=0;i<N;i++) begin...It creates and unnamed block. If you $display("%m") in the block it is called "...unmblkX" where is an integer.If I try to name...
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ncsim: *E,CLNAIA: Cannot call system tasks/functions while analog engine is...
Hi,here is my simulation log excerpt:ncsim> uvm_config_db -trace onncsim: *E,CLNAIA: Cannot call system tasks/functions while analog engine is interactive. while executing"call tcl_uvm_config_db 1...
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How to get the value of a string when using the string in a hierarchical path
Hi all Is there a way to use the value of string variable in systemverilog. I have a text file with the pin name and the value to be driven to that pin, on each line.There are around 50 pins....
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ERROR(ORCIS-6250): ODBC Error (Timeout Query)
Hi Guys, our Orcad 16.6 CIS search parts in a view running on an sql server.Often, when we try to search part we get the following timeout error:ERROR(ORCIS-6250): ODBC Error Code: -1Description:...
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Why it must have virtual interface initialized for an embedded covergroup...
Refer to the code as below, assignment of vif in build_phase() or connet() will result in different behavior. Anyone can explain a bit for this?Thanks.class apb_cov extends uvm_component; virtual...
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Is it a must to declare with keyword 'virtual' when define a task in a child...
Look into the code as below, the task whoAmI() is not declared using 'virtual', but when calling it from class B, it actually get B's task executed. Then it seems that the 'virtual' keyword is not...
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How to tell which test(seed) contributes to a specified coverpoint?
From the imc tool, we just know whether a coverpoint has been covered or not. Moreover, is there any way to check which test case just contribute to a coverpoint?Thanks.
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ncsim *N COVAUO message
Look into the ncsim log below, the covergroup instances, through are in the same covergoup type, do have their own names. Then why ncsim still output such *N message? Is there any potential risk, or...
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Display signals in Simvision
Is there a simple way to display all probed signals in Simvision?I have 21000 signals probed during the simulation and dumped to shm file. I want to display them all in simvision, but don't want to...
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How to avoid compiling Verilog/sytemVerilog views every time you netlist (AMS)?
Hi,I would like to know if is possible to avoid compiling the Verilog/sytemVerilog views every time you generate an AMS netlist in ADE-L (based on a config file with a sytemVerilog template).The...
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*E,SOSSZI Slice size for streaming concatenation expression has an illegal value
Hi,As I attempt to perform stream operation as below,bit[3:0] v_b[16];bit[31:0] v_a;v_a = { << $size(v_b, 2) {v_a}};It will give the error message "*E,SOSSZI Slice size for streaming...
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lib.map load order anomaly
I encountered the following anomaly:If my lib.map contains these clauses in this order: library mapped "{mapped netlist}"; library rtl "{behavioral model #1"; library rtl "{behavioral model #2";...
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Embedded cover group got started automatically?
Hi,I've defined a covergroup in a class and then instantiate an object of that class. Usually it needs to call start() method to start coverage collection.But I just found that covergroup exists in the...
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Substitute instance in netlist with wrapper
Hi all,I have a netlist with an instance of my rtl. As verification engineers we often find the need to add some (systemverilog) interfaces next to the rtl and the way we do it is to modify the netlist...
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How to accelerate ncelab phase when invoking irun?
Hi,Below is part of the irun log file which summarizes the time costs for each phase while compiling my ENV. Obviously, most of the time is consumed in ncelab phase, is there any way to optimize the...
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How to get the preprocessor output from irun?
I've tried irun -svpp But I was told that is is deprecated in the latest version.Is there any way to check the preprocessor output in irun?Thanks.
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NCSIM problem during functional simulation with Vivado
Hi all,I have a design in Xilinx Vivado 2017.2. The design work well with Vivado simulator and on board.But when I simulate the design with NCSIM(Version 15.20.026), interconnect give Decode error...
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ncvlog: *E,WKLNDF error
Hello,While doing Incisive simulation, I am getting the following error when using the AMS Unified Netlister option with irun from ADE-L netlister:ncvlog: E,WKLNDF (/home/........../chip.vams, 22|5):...
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