#ifdef #else #endif inside module instantiation in Verilog

Hi all, 

             I am trying to reverse engineer an open source verilog code for learning purpose. The code has some similar structure as below(please ignore my syntax errors) 

                         module tb_trail();

                              ....

                              test dut (

                                   .a(out)

                                   .b(in1) 

                                #ifdef TRAIL

                                     .c(in3) 

                                #else 

                                      .c(in4)

                                #endif 

                               );

             I have some basic knowledge in Verilog, and compiling it with INCISIVE. But when i try to compile the above module, I am getting error for missing either left or right parenthesis (*E,EXPLPA).

            Wondering, where is my mistake. Does INCISIVE(irun) supposed to understand those statements? is there a runtime option i need to specify to clear it? for your info, the definition for "TRAIL" is found with *.vh file  and I included it with -incdir option, and also added -vlog_ext +.vh to my run command

            Could someone help? 

Thanks in Advance! 

Aarthy