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History of SPECTRE
In an attempt to further my knowledge about Cadence and it's great tools I am seeking help form the community to find out where exactly the name SPECTRE comes from.A bit of research on the web gives...
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UVM Scoreboard and functional coverage model
Hi,I have reference model of design implemented in my scoreboard.Now for functional coverage how should I utilise this reference design from scoreboard?Or Do I need to code same reference design inside...
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SVA: What is supported and what is not...
Hi,I am trying to get a handle on what features of SV 2009 are unsupported.As an example, I was trying to use the $inferred_clock and $inferred_disable keywords, and getting compilation errors.Can...
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SystemC linking issues (Ubuntu >= 16.04)
I have an issue with ld during the linking process in SystemC environment.I would like to know if someone knows any workaround or idea to solve this issue!? Thank you.OS: Ubuntu 16.04 and 16.10The...
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Where can I access the "Specman Integrators Guide" in the cadence forums
Hello,This is probably a lame question.I am trying to develop some Verification Infrastructure in Specman and I am using a local copy of the Specman e Language reference manual which keeps referring to...
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Compile time ,elaboration time and simulation time calculation while running...
Hi, I'm looking for knowing on how to get the information on how much time consumed during compile,elaboration and simulation phases for any test in IRUN.If there is any switch please provide...
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Getting error while running dpi-c functions with SV code
Hi all,I am first time using dpi-c functions in my sv code.When I am trying to call dpi-c functions within sv code using irun command(irun -sv test_c.c test.sv).I have tried ncverilog,ncelab,ncsim also...
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Enabling UVM debug in simvision
Hi ,I came to know that there is a way to enable some uvm debug options in simvision. Can someone let me know what are the switches that needs to be enabled for this.Thanks,DN
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VPI: vpi_iterate does not access internal nets in SV code despite vpiNet
my vpi_iterate cannot access internal signals but the ports. Please help. Cadence Incisive version is 15.20.017.I have following module (in SystemVerilog):module my_block (input logic a,input logic...
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Performance difference between API (PLI/VPI/DPI), TCL, Verilog functions...
Subject explains.During simulaton runtime, there are three ways to read values of signals:Option 1: accessing objects through TCL command find and reading their values with the TCL command valueOption...
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System task output redirection
Is it possible to redirect the output of a system task, such as stacktrace, to a string in SystemVerilog?
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W,imc.license.analysis_failed: Failed to check out 'Affirma_sim_analysis_env'...
Hi,imc does not work on my computer but it work on other computers.On my computer, lmstat -a:Users of Affirma_sim_analysis_env: (Total of 2 licenses issued; Total of 0 licenses in use)Users of...
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How to map tests in vsif to vPlan items
Hi All,anybody has experience with mapping tests to vPlan in vsif file? I am using the vManager Client (15.20.s010)! In the vsif file I use the attribute vplan_ref to map a test to a TC item in the...
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Need help in identifying pending Objections in Specman
Hi,One of my Specman tests hangs in simulation because one of the component units that raised Objection did not drop it correctly.I was able to find out approximately which instance did that using...
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Problem with #(delay) in assign statement
While trying to model combinational delay in systemverilog the following was observed.The below code didn't workassign #(50ps) b = a;b was always x state.But the below code worksparameter real del =...
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Where does irun search for source files to generate implicit libraries?
From the ncvlog.log I seeUsing implicit TMP libraries; associated with library worklibGenerating native compiled code:... ...thereafter a library directory named inca.<my_lib> was built under the...
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Simvision doesn't always save waveform formatting
Hello, I'm running into a very frustrating issue/bug w/ the waveform viewer in Simvision where the waveform display formatting is not always saved to the svcf file when the "save command script"...
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SV: How to name an unnamed block
If I create a variable in a for-loop: for(int i=0;i<N;i++) begin...It creates and unnamed block. If you $display("%m") in the block it is called "...unmblkX" where is an integer.If I try to name...
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ncsim: *E,CLNAIA: Cannot call system tasks/functions while analog engine is...
Hi,here is my simulation log excerpt:ncsim> uvm_config_db -trace onncsim: *E,CLNAIA: Cannot call system tasks/functions while analog engine is interactive. while executing"call tcl_uvm_config_db 1...
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How to get the value of a string when using the string in a hierarchical path
Hi all Is there a way to use the value of string variable in systemverilog. I have a text file with the pin name and the value to be driven to that pin, on each line.There are around 50 pins....
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