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K-i-t-c-h-e-n-s For Sale Exeter Area UK
K-i-t-c-h-e-n-s For Sale Exeter Area UK Go to h-t-t-p-:-/-/-w-w-w-.-c-h-e-a-p-k-i-t-c-h-e-n-s-.-u-k-.-c-o-m
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I am checking the code coverage for one of my Module's testbench, but the...
I am checking the code coverage for one of my Module's testbench, but the expression coverage is appearing as "n/a" , why is that so ? there are if-else & assignments in the RTL... how do I enable...
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[AHB eVC]How to send transfers with no IDLE cycles
Hi, I want to send multiple SINGLE bursts with no intervals in between. like 2-2-2-2-2-2-2-2...However, when I use the following source code, I got a couple of IDLE cycles like 2-2-0-2-2-2-0-2-0-2...,...
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[SV] Constraint solver issue
hellobelow is a class I use for randomize some settings of a ADC controller RTL.I got the following error stop -create -name Randomize -randomizeCreated stop Randomizeassert (...
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Explicit wire declaration by Virtuoso netlister
Hi all. When I generate a verilog netlist out of virtuoso ncverilog netlister I see that implicit net s(those internal to modules) are not esplicitly declared. Is there any way to force the netlister...
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How to generate illegal AHB transactions using eVC
Hi, I am trying to generate some illegal AHB transactions to test how the DUT behaves.For example, I generated a WORD transaction, then changed the 4-byte aligned address to one that did not align.I...
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[AHB eVC]Unexpected 1ps delay on BFM
Hi, Another question on AHB eVC.For some reason, when the master agent drives the AHB signals (to be specific, HSIZE and HADDR), sometimes there will be a 1ps delay(clock period is 3.75ns).It may or...
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Including `defines with ncvlog netlisting
All,This is using IC6.1.7-64b.500.6. I have a mixed-signal hierarchy in which several of the blocks have both schematic and Verilog cellviews. The Verilog cellviews are purely digital representations...
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Exclude a net from block coverage
Hi All,Incisive coverage pragmas works great to turn off coverage on a certain block of a code.However I was wondering if we could exclude a group of nets from being covered?For example, As shown...
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Problem with user define net types resolution functions
Hi all,I have defined a net in this way:typedef struct{real V;real I;} EEstruct;function automatic EEstruct res_EE(input EEstruct driver[]);foreach(driver[i]) begin.....to debug my resolution function...
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JasperGold connectivity check
I am trying to check this part of codealways @(posedge clk or negedge rstN) begin if (!rstN) last_phase <= 1'b0; elselast_phase <= sample_grant;endIn this am trying to check only if condition...
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JasperGold connectivity check.
I am trying to check the following always @(posedge clk or negedge rstN) begin if (!rstN) last_phase <= 1'b0; else last_phase <= sample_grant;endIn the above code i am trying to check the if...
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[IUS] Code profiling
Hi thereI'm asking how (if?) to perform code profiling: I have a simulation which stops and does not terminate due to excess events generation. Since the design is way too complex I am trying to chase...
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Verilog instantiating SystemC (generated using Verilator). irun error: Could...
Hello,We are trying to instantiate SystemC module generated using Verilator tool and simulate using irun.We have a sample counter DUT and we are running 3 configurations.(1) Pure VerilogThere is top.v,...
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Generate an index to an ungeneratable list of struct
Hi,How do i generate an index to a list of struct with constraints.For example i have the following struct and list:struct se_cte_free_mem_area_s{ !address_start : u64_t; !address_end : u64_t;...
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Incisive Enterprise Manager Blank Screen
Hello,I am running Incisive Enterprise Manager on a tiling window manager (dwm 6.0) and whenever I run vmanager, the second window that comes up (the actual incisive enterprise manager) is always a...
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Generate min/max values on modified bitslice scalar
Hi,How do i generate min/max values on modified bit slice scalar?For example i trying to do the following and Specman fail during generation:"gen_address(alignment : u64_t) : u64_t is {var bits_to_zero...
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Error in UVM code
Hi,I'm getting the following error when running the UVM code present in the following location. There is a sequence_item example which is present....
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Optimization in concantination of scalar generation
Is there any performance gain on using the following concatenation:" address_upper_bits : uint (bits : 17); address_lower_bits : uint (bits : 47); address_upper_bits in [0x0,...
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BlackBox RTL/GateLevel
Hello! I would like to create two black boxes one in RTL and another in GATE LEVEL, it can also be one like black box and the other not, however the two DUTs have the same instance inside the module...
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