VPI: vpi_iterate does not access internal nets in SV code despite vpiNet

my vpi_iterate cannot access internal signals but the ports. Please help. Cadence Incisive version is 15.20.017.

I have following module (in SystemVerilog):

module my_block (
input logic a,
input logic b,
input logic c,
output logic z
);

logic intermediate_signal;

assign intermediate_signal = a & b;
assign z = intermediate_signal & c;

endmodule

I have written a VPI routine to grab all the signals in the block above:

#include <sv_vpi_user.h>
#define NULL 0

int dut_dump (char *str) {

vpiHandle handle_scope_iterator;
vpiHandle handle_scope_object;
s_vpi_value object_value;

vpi_printf ("Scope: %s\n", str);

object_value.format = vpiBinStrVal;

handle_scope_iterator = vpi_iterate(vpiNet, vpi_handle_by_name(str, NULL));

while (handle_scope_object = vpi_scan (handle_scope_iterator)) {
 vpi_get_value (handle_scope_object, &object_value);
 vpi_printf ("net: %s, value %s\n", vpi_get_str(vpiName, handle_scope_object), object_value.value.str);
}

 return (0);
}

When I instantiate the block my_block in a testbench and call the dut_dump in the testbench,

module tb ();
...
my_block dut (...);
...
initial begin
....
dut_dump("tb.dut");
...
end

endmodule

Simulation gives following:

ncsim> run

Scope: tb.dut
net: a, value 1
net: b, value 1
net: c, value 1
Memory Usage - 29.3M program + 25.1M data = 54.4M total

It does not iterate the internal signal intermediate_signal.

• Where is my mistake?
• Is VPI implementation for SystemVerilog in Incisive extended?
• Do I use the correct header name?
• Do I need a special switch to compile/elab/sim at Incisive?