While trying to model combinational delay in systemverilog the following was observed.
The below code didn't work
assign #(50ps) b = a;
b was always x state.
But the below code works
parameter real del = 50ps;
assign #(del) b = a;
I feel this is a bug in irun.
File: systemverilog
irun argument -TIMESCALE 1s/1ps
Version irun: 15.20-s008