Forcing Verilog signal simple_port with pli_access == TRUE in Specman

Hi,

I am working in Specman e and I am trying to force a signal value to a simple port that has its pli_access constrained to TRUE. I am unable to remove the pli_access constraint.

If I use the force keyword, I get a specman error message telling me that force is unsupported with pli_access set to TRUE. Unfortunately, I cannot just do a normal assign because I need the value of this signal to remain until I explicitly release it later.

All of my work arounds don't seem to work. I may need to operate on a signal that is wider than 32 bits as well...

Thanks for your time.

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