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Binding systemverilog modules (module ports' directions)
Hello,I'm using some binding modules in sytemverilog VIP. They are binded to VHDL modules.The systemverilog modules' ports are all defined as logic without specifying direction (input, output or...
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coverage on e Temporal checks
Hi I am trying to get functional coverage on the temporal checks in my e based verification environment. I added the specman_pre_command "configure cover -collect_checks_expects=TRUE" in my...
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Setting time resolution using irun
Can I change time resolution using iruns scripts?Command: irun -input setup.tcl Script: database -open waves -into xxx.shm -default -eventprobe -create -all -depth allrun 2ms Now I have got on my...
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Z state check inside SV
I am using cadence irun to run the mixed signal verification. I am trying to see if real value i am getting is has open drained or not. How do I check Z state of real value in testbench.
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How to implement soft reset or functional level reset in vr_ad register model?
Hi all,In my project in the register model i have some fields which are sticky i.e. they are not effected by reset.For such fields how to implement in vr_ad? If it is possible, is there any chance to...
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ncsim: *F,INTERR: INTERNAL EXCEPTION
Hi, Sir, I meet the following error : $xana_source in ...........ncsim: *F,INTERR: INTERNAL EXCEPTIONObserved simulation time : 0 FS + 0TOOL: ncsim(64) 11.10-p001HOSTNAME: shacs201OPERATING SYSTEM:...
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Filtering UVM info messages
Hi,I would like to ask if there is a way of filtering uvm_info messages output during simulations.I am interested in messages coming from one particular uvm_component.Does SimVIsion have a feature like...
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Simulating basic Log Amplifier and Antilog Amplifier using diode as well as...
I'm learning the basics of Cadence OrCAD 16.6 Lite. I want to design and simulate the basic Log Amplifier and Antilog Amplifier circuits both using diode as well as transistor. I'm able to design these...
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Error while invoking Cadence IC615 virtuoso
HiI have installed Cadence IC615 in FEDORA 15. While invoking it by typing virtuoso, its giving folllowing error"ERROR: Can not find any 32 bits or 64 bits executable version of "virtuoso"" Can you...
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ncsim: *E,IMPDLL: Unable to load the implicit shared object
Hi,While running simulation , i am getting the below mentioned error .Can anyone help me to fix this error.ncsim: *E,IMPDLL: Unable to load the implicit shared object.OSDLERROR:...
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ncsim: *E,IMPDLL: Unable to load the implicit shared object.
Hi All, anyone encounter below issues when running OVM ? how to resolve this issue ?ncsim: *E,IMPDLL: Unable to load the implicit shared object.ThanksSimon
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changing the name of waves.trn file
Hi,Does any one know how to change the name of waves.trn located in waves.shm directory during simulation ?Is there a command-line option that can be passed to irun to do this ?This is because every...
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One hot assertion in RTL
Hi,What is the best way to add one hot assertion on a bus in verilog? Ex: Wire [9:0] one_hot_wire; Only one of the bit of this wire is supposed to go high in the simulation otherwise it should fail....
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ncelab: *W,MXWARN: Reached maximum warning limit for 'CUVWSP'(1000)
Hi,During gate level simulation i am getting below mentioned warning.ncelab: *W,MXWARN: Reached maximum warning limit for 'CUVWSP'(1000)After this ncelab: *F, INTERR EXCEPTION is coming. How to ignor...
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Gate level simulation flow with cadence
Hi,I am new to gate level simulation.Can anyone guide me for steps involving gate level simulation using incisive simulator.I am using irun insted of ncsim and i have a netlist and a sdf file.Please...
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Gate level simulation with netlist and other RTL files
Hi,In my top level environment there are several modules are instantiated and one of the module is replaced by netlist.i am facing *F,INTERR: INTERNAL EXCEPTION.Netlist should be top file or it can be...
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Exclude signal in IMC in command line
Hi,I met some issue to exclude signal in IMC.In fact, I'm using the syntaxe given in the help example of IMC HELP as follow:exclude -inst lib.inst_a(rtl):inst_b:inst_c (WORKING THE INSTANCE IS...
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Accessing vplan attributes from console
Hi All, Does anyone know anything about the API to access vplan attributes from the console or from an e program ? Specifically I want to be able to output this data in an arbitrary text format. I...
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Assertion detect *WORNG* fell of line due to gated clock
Assertion detect *WORNG* fell of line due to gated clock Simulation assume line was high and on the posedge of clock the line is constant low and detect it as FELL and assertion is active due to that...
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Gate Level Sim - SDF annotation debug
Hi, I am trying to annotate an SDF to my gate level synthesis netlist and I am seeing some strange behaviour. When I annotate using just the netlist, cell_lib and sdf , everything works fine. However,...
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