Assertion detect *WORNG* fell of line due to gated clock

Assertion detect *WORNG* fell of line due to gated clock

 Simulation assume line was high and on the posedge of clock the line is constant low and detect it as FELL and assertion is active due to that and cycle after fail!

 assert property ( @(posedge TxByteClkHS) disable iff(!rst_sys_n) 

      $fell(TxRequestHS) |=> $fell(TxReadyHS) );  

Tought to add ##1 cycle delay before every assertion, but the solution is not very good.