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Getting vhdl constants in system verilog
Hi, I need to re-use the constants and record type variables in system verilog which are defined in vhdl DUT (in a separate package file). I could not find the idle way to do this task except...
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convert string to list of bit
I'm looking for a way to read a file containing (HEX) numbers.For each file I read, the width of the data is different (can be more than 32/64/128 bits).So I'm looking for a way to convert the string I...
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SOC connectivity check
The format for the xls to enter connectivity isn't very clear in the user manual. Can anyone give me a sample? Thanks.
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Bandgap voltage reference problems
Hello!I'm trying to make this band-gap ref. circuit to work but, up to now, i haven't reached the right result. I've already checked the circuit, but i couldn't find any misconnections on it.Can you...
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Issue with merging coverage
HiI finished running a set of simulation tests with coverage, and now I am trying to merge the coverage, but I got the following error. I am able to load individual test, but I can not merge all of...
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Passign commands to ncelab using irun
Hi,I'm using the irun command. I want to pass an option -binding to the ncelab. How do I do this?Thanks.
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Binding vhdl output ports and sv assertion module input ports in cadence...
Hi,Is there a way to bind vhdl outputs with my SV checker module input ports? And also how do i access vhdl ports from my sv testbench? Thanks,Rajay
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Engine for IFV
Hey, The automatic assertions take a very large time to run as my design is huge.Could anyone tell me which is the best engine to use so that I can fasten this process?Thanks.
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SOC connectivity checks
Hey, I entered connectivity information onto an xls and generated assertions on IFV. These take a very long time to run. If I write similar assertions myself, it runs faster. The only difference...
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Adding automatic assertions in IFV?
I've used the assertion -add -automatic command.But this doesn't add any assertions, but gives a warning saying: Session does not have any assertion.It runs user-defined assertions. Also, when the...
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can we have debug statements displayed with IFV tool
Hi, Iam doing formal verification om certain block and iam having some of the display statement in source module.WIll those display statements displayed when i do simulation using IFV. Ex:- iam having...
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How to probe VHDL function variables in ncsim?
Hi, I need to view the variables used inside a function in simvision waveform viewer. How to add a probe to view these variables in the viewer?Thanks,Venkat
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which all signals need to be initialized in a module
Hi Iam doing formal verification,Iam getting so many signals unitialized.Iam not understanding which signals we should initialize.How to know which signals we should initialize in a module.
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SystemVerilog Assertions: Property Library
Hi Everyone!Im new in this whole SV Assertions world, and Im having some troubles trying to define a "property library". Basically, what I want to do, is to have all my properties definitions in a...
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convert string to list of bit
I'm looking for a way to read a file containing (HEX) numbers.For each file I read, the width of the data is different (can be more than 32/64/128 bits).So I'm looking for a way to convert the string I...
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what do you mean by assertion block
HiIam having some of the assertions result as block.What do you mean by block and how to make those assertions passing or failing. ThanksBharath
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how to create System C Wrapper over system verilog..
Hi, We need to create system C wrapper over System verilog[SV Environment Database]. if any body have idea please share it... Note: SystemVerilog Database which is in SCEMI MODEL.......
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Can I replace the test pattern after restart the snapshot
In my code simulation ,it must be have boot action at the beginning of process. I want to skip it to save time, so i use snapshot funtion.But my test pattern is putting on TOP module. The snapshot file...
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Super Linting advantages
Hello,Can anyone tell what the advantages of the Super Linting features in over the SpyGlass Linting?Thanks.
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IUS 10.2 irun - how to re-run an already compiled snapshot
Under the old 3-step process (ncvlog+ncelab+ncsim), I could compile the testbench once. Then call ncsim multiple times to run the sim again(without recompiling.)How do I do that with irun? What are...
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