Quantcast
Viewing all articles
Browse latest Browse all 1091

Managing "delta" delays with VHDL/PSL

Hi,

We are using VHDL flavour PSL with a VHDL design, and are seeing assertion failures due to VHDL delta delays.

I read that SystemVerilog has solved this problem by checking all assertions in a new simulation phase. Is there any way of forcing ncsim to do this for a VHDL design?

Thanks,

Steven

Image may be NSFW.
Clik here to view.

Viewing all articles
Browse latest Browse all 1091

Trending Articles



<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>