Why do I get an error when I try to generate (any) system Verilog module?

If I try to make a new cell view of type system verilog from the library manager GUI I systematically get this error (the content of the module does not matter):

F,AMSASV: The -ams and -sv options cannot be used together.

Which means that I cannot get a symbol and so on...

I checked all my options and I don't see why the -ams option is kicking in.

Any help woudl be greatly appreciated!

Thanks,

Giorgia