Hi:
Reg 2 has two clocks available, which one is used is determined by the a signal.I want to do a cross-clock domain path analysis from reg 1 to reg 2 When reg 2 uses clk 1，and use “check_cdc -signal_config -add_constant {{a 1'b0}}” could to set a to zero , But this value will not be passed to b（Q port of reg 0）, Jaspergold will recognize that reg 1 and reg 2 are in different clock domains，But in fact reg 1 and reg 2 are in the same clock domain
How should I modify the jaspergold script？
thank you！