Instantiate SystemC module in SystemVerilog module with real/double ports

I would like to instantiate a SystemC module inside a SystemVerilog module with real/double ports.

Here is some source code:

// file model.h:
#include "systemc.h"
class model : public sc_module {
public:
 sc_in <double> inval;
 sc_out<double> outval;
 SC_CTOR(model) : inval("inval"), outval("outval") {
   SC_METHOD(run);
   sensitive << inval;
 }
 void run() {
   outval.write(inval.read());
 }
};
// file model.cpp:
#include "model.h"
XMSC_MODULE_EXPORT(model)
// file model.sv:
module model (inval, outval )
 (* integer foreign = "SystemC";
 *);
 input var real inval;
 output var real outval;
endmodule
// top.sv:
module top;
 real inval;
 real outval;
 initial begin
 inval = 2'b0;
 #10 inval = 1.0;
 #10 inval = 2.0;
 #10 $finish;
 end
 model test (inval, outval);
endmodule

Here is the command to compile and run:
xrun -sysv top.sv model.sv -sysc model.cpp -top top

I get an error:
 input var real inval;
 |
xmelab: *F,SCVREG (./model.sv,17|21): Found a Verilog output register in the shell 'model'.

If I change the port types to [1:0]/sc_uint<2>, everything works.

How can I connect real/double ports without having to resort to $realtobits, etc.

Thank you.