NCSIM problem during functional simulation with Vivado

Hi all,

I have a design in Xilinx Vivado 2017.2. The design work well with Vivado simulator and on board.

But when I simulate the design with NCSIM(Version 15.20.026), interconnect give Decode error during first register access from an AXI Master. There is no error in simulation flow (compile & elaborate). I used same design & test bench for both Vivado and NCSIM simulation.Also I have compiled the libraries and mapped during simulation.

I know this information is very limited. What could be a primary reason for this problem? 

Regards

Anjo