Hi,
Is there a way to bind vhdl outputs with my SV checker module input ports? And also how do i access vhdl ports from my sv testbench?
Thanks,Rajay
↧
Channel:
Cadence Functional Verification Forum
X
Are you the publisher?
Claim or
contact us
about this channel.
X
0
Channel Details:
- Title: Cadence Functional Verification Forum
- Channel Number: 3711457
- Language: English
- Registered On: July 11, 2012, 10:00 pm
- Number of Articles: 1069
- Latest Snapshot: November 5, 2024, 11:09 am
- RSS URL: http://feeds.feedburner.com/cadence/community/forums/30
- Publisher: https://community.cadence.com/cadence_technology_forums/f/functional-verification
- Description:
- Catalog: //kitthoge4.rssing.com/catalog.php?indx=3711457
© 2024 //www.rssing.com