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SimVision - Source browser doesn't opens the source code

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Hi,

The source browser tab doesn't display the source code of the highlighted design unit, while the source code file can be opened manually from the file menu. As I dug into the problem, I realized that the source browser decends into another directory rahter than the courrent work directory. Can anybody help me solving this small issue which is very irritating and if the design has been made by someone else and my job is just to debug it, it makes harder to locate the declaration of the highlighted design unit.

I am using IUS-8.20.023.

Cheers, 


Coverage results over the time (RTL)

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Is it possible to track the coverage results over the time? For bug detection, it is well accepted that the rate at which bug are detected approximates an exponential decay. That is at beggining is should be easier to detect bug, then it becomes more an more complicate. We can distinguish between easy and hard-to-detect bugs. The trends can be depicted in this chart:

Bug detection
  ^
  |--------- 100% ------------------------------
  |                                    *    *   *
  |                              *
  |                       *
  |                *   
  |           *
  |       *   
  |    *                      
  |  *                        
  |*
  |-----------------------------------> Time

 Can I register toggle or block coverage at RTL with timing information for printing a similar chart? 

Toggle, block, statement coverage... what else?

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Incisive allows to measure toggle, block and statement coverage at RT level. Is it possible to use other coverage metrics for RTL descriptions? Does Incisive provide a fault injection feature?

ncsim -out directive

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Hi,

I created a sub-directory inside the main directory where I am invoking Incisive to dump all the files generated using "-out" argument. In my design, I need to pick values from a certain file from the main directory. Now the ncsim looks for that file into the sub-directory I have created and obviously its not there. Is there any way to specify such argument in the Makefile attached alongwith? 

UniPro eVC integration

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Hi,

I'd like to integrate the CDN UniPro eVC to a verification component, that will be reused multiple times. I noticed that each layer in the UniPro stack communicates upwards and downward via method ports. My idea is to reuse the upward method-ports of the transaction layer to communicate with the UniPro eVC (drive, monitor the UniPro operation from a higher layer). To do so , I need to know the definition of the method-type of each port, but I could not find it in the documetation of the eVC.

Is there a way to get information about those method ports?

Can you suggest better way to integrate the UniPro eVC? 

Best Regards,

Peter 

specman clock

Warning in Toggle coverage exclusion

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Hi ,

I am getting the following warning when trying to exclude toggle coverage.

 ncelab: *W,PSEFDM: The pattern "sig_1" specified on line 7 of file "toggle_exclude.cf" did not result in exclusion of any signal(s).

 I am loading the exclude file by set_toggle_excludefile -bitexclude toggle_exclude.cf

There is no recursive exclusion of same signal . Also deselect_coverage option is not used . Still I am getting the warninig . But in the report the bit is excluded . Please help .. Thanks in advance ..



 

ATPG for RTL

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Does Cadence provide any ATPG for RTL descriptions? The goal should be to maximize some coverage metrics (e.g., toggle, block).

Cadence lint HAL tool

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CG cell is not detected as gated clock, can u help me?

i hv tried with below setting, but it didn't work.... 

params GTDCLK {identify_clock_gating_cell="no"}

FSM coverage (RTL from CtoS)

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I am trying to measuring FSM coverage of RTL code that tis generated with CtoS and co-simulated with its original TLM testbench (CtoS generates some wrappers for doing that).

I am passing -COVFILE covfile.ccf as an argument of ncsc_run. The covfile contains:

select_coverage -all -instance sc_main.channeldownsampleCb.tlm_instance.m_dut_vlog

at the end of the simulation I can visualize toggle and block coverage (iccr)  but not FSM coverage. 
 
During simulation I get the warning:
 
ncsim: *W,COVUSC: Unsupported SystemC module (worklib.sc_main) specified for coverage 
 
What is my error?

ncelab ncutilities E,BUILDF

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Hi all,

 

Switching from release 10 to 12.2, I've found some problem with testbench which uses nc utilities. 

ncelab (version 12.2) with option "-update" exit with  :

 --------------------------------------------------------------------------------------------------------------------------------------------------------------------- 

ncelab(64): 12.20-s007: (c) Copyright 1995-2013 Cadence Design Systems, Inc.

Updating: package NCUTILS.NCUTILITIES (AST)

/cadence/IS12.2/tools/inca/files/NCUTILS.src/ncutilities.vhd:

ncvhdl_p: *E,DLPAKW: Attempt to write package ncutils.ncutilities (AST)

into a read-only library.

         errors: 1, warnings: 0

ncupdate: *E,BUILDF: Rebuild of unit package NCUTILS.NCUTILITIES (AST) failed.

entity worklib.tb_ncutil (AST) is already up to date.

ncelab: *F,DLUPFL: Update failed for entity WORKLIB.TB_NCUTIL (AST)

(unable to update).

 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------

 

I didn't find clues on the web or in the docs,

 

Thanks,

Luca

 

IFV Dead code check fail

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In Formal properyty checking deadcode assertions and property getting failed.What is the meaning of these getting failed.How we can pass them.

How to debug this 

how to reduce explored

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Hi,

 

Iam using IFV for formal property checking and i have some of the assertions/Property explored.How to make them either pass/fail.

 

Thanks

Bharath 

Gate Level Sim - SDF annotation debug

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Hi, 

I am trying to annotate an SDF to my gate level synthesis netlist and I am seeing some strange behaviour.

When I annotate using just the netlist, cell_lib and sdf , everything works fine. However, when I try to annotate using the testbench and providing the full scope to the netlist within the verification environment (SCOPE=test_env.<scopetodigtop>.udig_top), I see thousands of 

SDFNEP, SDFNET errors. The paths and timing checks which ncelab is complaining about definitely do exist in the cell_lib verilog, and the scope is definitely correct. I have tried modifying the scope just to make sure that it was correct and with anything apart from these settings the annotator complains that the scope is incorrect and refuses to proceed.

What am I missing and what is the best way to debug this ?

I have tried versions incisiv/11.10.011, incisiv/12.10.011 and incisiv/12.20.008 

thanks

Andy 

run IFV Xcheck property

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Hi

 

Iam doing XCheck property checking.Now instead of running all the properties,I want to run only one XCheck property in IFV .

 

How to prove single XCheck assertion. 

 

 

 

 


uninitialized state elements

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Hi,

I have some of the stateelements uninitialized in my design.What could be the reason they are uninitialized.What will be the problems we will be having if we have uninitialized state elements. 

want to understand with an example what are unitialized elements and debug.

 

Thanks

Bharath 

DIVA LVS Problem After Installing Assura

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Hi, I'm a beginner and i'm trying to explain my problem as best i can. I use IC615 and Assura 41. After installing and putting Assura into my system (set environment variable ASSURAHOME) diva does not work properly. After i go from verify/LVS.., first there's some buttons missing from the diva LVS window, there're like half buttons missing from the window. The extracted view was matched with the schematic before. But after installing assura i could not use verify/LVS to match any cell. And when i ran lvs i get something like this:

 "Unrecognized input "No" in the netlist"

 In the netlist of the layout it says a bunch of

"No element format property found for element /+1924" "No element format property found for element /+1923"...

It's like the netlist could not be recognized any more by diva. I thought this is a problem caused by Assura. i deleted the environment variables(ASSURAHOME) to block assura. But the problem is still there. 

I mean is it normal that after installing assra that diva changed? Or after installing assura all the diva rule file has to be converted to assura?

Thanks in advance 

Create/Import Verilog-AMS Cell View

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I have a problem with CADENCE, importing or creating a VERILOG-AMS file.

I have to import a device model which has been developed in Verilog-AMS (I have a file with ".vams" extension).
In the following, I try to summarize and explain what I have done and tried.

1) I tried to import my file through the "IMPORT" tool of CADENCE but it seems to be impossible. I have this error: "The parser ncvlog failed to parse the text file. Refer to the file 'ncvlog.log' for compilation messages and errors". I don't know if the problem is related to the verilog editor/compiler named "ncvlog".

2) I tried to use the tool "NC-VERILOG". Also in this case, when I try to generate the netlist from the "verilog-ams" file, I have the following error:"ERROR (OSSHNL-103): Unable to open the design, library 'GMR_Model', cell 'Test_2', view 'verilogams'. Ensure that the cell view exists or the SKILL variable, simDcmFilePath, is correctly defined".

 

3) I tried to generate a new cell view creating a "Verilog-AMS" file with the "modelwriter" of Cadence or creating a "VerilogAMSText" utilizing a Verilog-AMS editor of Cadence.
Once again I have problems because, in the first case, the ModelWriter of Cadence works fine but it is possible to create "verilog-ams" files only starting from a list of examples, without any possibility to change something. The generated example can be simulated with good results. On the contrary, when I try to generate a new "VerilogAMSText" utilizing a Verilog-AMS editor, a file "verilog-ams" is created, but not opened automatically with the editor. I have this warning: *WARNING* editFile: sh: xterm: command not found.

I tried to set (manually) the editor for "verilog-ams" utilizing this command: "editor=<PATH of the editor>". I checked both "EXTERM" and "ncvlog". In the first case, setting: editor="/ic_tools/cds/IC.6.15.011/tools.lnx86/dracula/bin/32bit/EXTERM", when I try to generate a new file, the window of editor does not appears (probably the Editor doesn't work) and I have this error:/ic_tools/cds/IC.6.15.011/tools.lnx86/dracula/bin/32bit/EXTERM: error while loading shared libraries: libgdbm.so.2: cannot open shared object file: No such file or directory. In the second case, setting: editor="/ic_tools/cds/IC.6.15.011/tools.lnx86/inca/bin/ncvlog", when I try to generate a new file, the window of editor does not appears (probably the Editor doesn't work) and I have no errors. However, in both cases, a file "verilog-ams" is created in the "view" column and it is only possible to open it in "read-only" modality. In this case, the file is opened through a windows of VerilogAMS-Editor without any possibility to modify/edit the file and run the compiler VerilogAMS.

 

Where is the problem? Is it related to Linux, the installation of CADENCE or other?

How can I do to create a Verilog-AMS view and then simulate it?
Thanks a lot.

How to make eManager run in "parallel"

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Hi,

is there any why to configure eManager to work in parallel.

to say,

i want eManager to take all test for given Vsif and to be able to run them on a predefine (by user)  number of stations (LSF - bsub).

currently, eManager is running the Vsif test by test serially on a single station.

Thanks in advence,

--Kobi  

 

 

Adding automatic assertions in IFV?

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I've used the assertion -add -automatic command.

But this doesn't add any assertions, but gives a warning saying: Session does not have any assertion.

It runs user-defined assertions. Also, when the command is run with this, it says 0 assertions added.

How do I rectify this?

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