Hello,

I have made a design, and after place&routing I want to study the timing report of the paths. This report I make trought the 'report_timing' command.

With the -format, you can specify what information you want to see in the timing report. I want to see the slack per node in the report. So basically I want to see also a column of the slack, which is basically the required time - arrival time.

The only slack I see is for the total path, and not for each node of the path.

Is there a way to show this information? I've tried also to specify in the -format, the slack, but it seems that I get only the slack back of the whole path. 

Dear All,

I'm trying to merge the coverage report of different test case of the same DUT but im getting an error saying.

Normal 0 false false false EN-US X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin-top:0in; mso-para-margin-right:0in; mso-para-margin-bottom:10.0pt; mso-para-margin-left:0in; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;}

Block coverage not merged - Checksum differs.  Data is projected in to the target model.

The steps for generating the coverage are:

1. Used the -coverage all option in the irun command "irun -coverage all"

2. Generated coverage for each test case in test_xxx folder.

3. Used the batch method to merge the each test case coverage into single coverage in coverage_log folder.

 Please refer the below error message and suggest me to slove the issue.

Normal 0 false false false EN-US X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin-top:0in; mso-para-margin-right:0in; mso-para-margin-bottom:10.0pt; mso-para-margin-left:0in; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;}

[bin]$ imc -batch merge_ncsim.cmd

imc: 11.10-p001: (c) Copyright 1995-2011 Cadence Design Systems, Inc.

Starting batch mode

imc> merge test_001/cov_work/scope/test/ test_002/cov_work/scope/test/ test_003/cov_work/scope/test/ test_004/cov_work/scope/test/ test_005/cov_work/scope/test/ test_006/cov_work/scope/test/ test_007/cov_work/scope/test/ test_008/cov_work/scope/test/ test_009/cov_work/scope/test/ test_010/cov_work/scope/test/ test_011/cov_work/scope/test/ test_012/cov_work/scope/test/ test_013/cov_work/scope/test/ test_014/cov_work/scope/test/ test_015/cov_work/scope/test/ test_016/cov_work/scope/test/ test_017/cov_work/scope/test/ test_018/cov_work/scope/test/ -out all -overwrite -metrics all

imc: *W,MGOPOW: The merge output directory cov_work/scope/all will be overwritten.

Merging IUS Coverage ...

----------------------------

Preparing target model ...

Reading model of primary run (test_001/cov_work/scope/test/) as initial model: test_001/cov_work/scope/icc_633670ed_00000000.ucm

Target model generated successfully.

Projecting ICC ucd data into the target model ...

test_001/cov_work/scope/test/:

  Data is projected in to the target model.

test_002/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_003/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_004/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_005/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_006/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_007/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_008/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_009/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_010/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_011/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_012/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_013/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_014/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_015/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_016/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_017/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

test_018/cov_work/scope/test/:

    "tb_sum_int.INST_TESTCASE" to "tb_sum_int.INST_TESTCASE": Block coverage not merged - Checksum differs.

  Data is projected in to the target model.

Writing output database cov_work/scope/all:

  Model: cov_work/scope/all/icc_633670ed_00000000.ucm

  Data : cov_work/scope/all/icc_633670ed_00000000.ucd

No Specman coverage databases found in the runs.

Total conflicts during target model creation: 0

Total items not merged                      : 17

List of conflicts non-merged items during target model creation report only when merge is run with "-message 1" option.

imc> load -run cov_work/scope/all

Successfully loaded run '/device/modules/sum_ctrl/verif/bin/cov_work/scope/all'.

imc> report -detail -type -html -all -out coverage_log/ -overwrite *

Output of report -html command sent to directory: coverage_log/

Thanks & Best Regards,

Chetz.

Hi,

    I'm trying to compile my UVM testbench which is having some package files. At the time of compiling common_pkg.sv file which is one my packages the tool encountering ERROR showing   "cannot open include file 'common_defines.svh'.

Can anyone suggest me the ways to avoid the above error?

Thanks,

regards,

mahee.

I am trying build UVC using IVB but IVB not showing Port definations dialog for Systemverilog-UVM where as it is showing it for UVM-e.

Please help me to declare additional ports in IVB.

 Hi all

I am looking for a way to get all the local variables within a specific method.

i didn't find an API function in rf_method  struct that do such operation.

i will happy if some one can show me how it is done.

Regards.

EM

Hi,

I have an Verification environment with and OCP MASTER eVC connected to a OCP complaint Slave (RTL). 

We are trying out simulate multiple read/write transactions using the OCP eVC api methods write() and read_resp() .

There are idle transactions between read/write. But if the idle delay is less than 10 cycles, we are getting an dut_error.

The error basically occurs in the read transaction that is issued after three back to back write transactions. When the read_resp() api is called, the READ sequence is executed but no transaction is appearing on the interface (as viewed on the waveform) as the previous writes are not yet completed but the BFM moves ahead with the read transaction.

I wanted to know if there are any restriction on the number of idle cycles between read/write transactions if we use the api methods or is it possible the issue the back to back read/write transactions without any idle cycles in between using the OCP eVC?

Thanks,

Navaneet

hi,

  i have few register in RGM which have only read access with sequential addresses. i can update the register(backdoor update) by writing the rgm pointer and register pointer and write function. but now i want to update those registers by address how can i do that?

regards

bhanu kumar

 Hi all,

    I am try to creating eRM Wrapper for  sv Environment. In that environment systemverilog tasks/function which is called from specman e methods. I have better knowledge in both Verification component. but i need how to interfere this both Verification component. if any body have an Idea about this. share your knowledge this will helpful for me to update

example code:

In Sv:

    function void m(bit [`ADDR_SIZE-1:0] addr,bit [`DATA_SIZE-1:0] data);

    $display("ADDR: %d",addr);
    $display("DATA: %d",data);
    $display("iam here");
    endfunction

In eVC:

 .......here, how can i call above systemverilog function ?....

Thanks & Bestregards,

selvavinayakam.na

This is based on the article in EE times http://www.eetimes.com/design/eda-design/4229801/Assertion-based-verification-in-mixed-signal-design vy 2 Cadence  authors. Another post similar to this used a VAMS test bench it seems http://www.cadence.com/community/forums/T/22576.aspx.

I am trying to implement this simple test bench in the following manner:

  // Module top.sv

module top;
var real r, xr, wr;
assign xr = 3.14;

ams_electrical_src e_s1(r);

// causes insertion of Electrical2Real connection module
ams_electrical_dst e_d1(xr);

// causes insertion of Real2Electrical connection module
ams_wreal_src w_s1(wr);

// Coercion of SystemVerilog real variable to wreal

endmodule

// Module ams_electrical_src.vams
`timescale 10ns / 10ps
`include "disciplines.vams"
module ams_electrical_src(e);
  output e; electrical e;
  analog V(e) <+ 5.0;
endmodule

 //Module ams_electrical_dst.vams
`timescale 10ns / 10ps
//`include "disciplines.vams"

module ams_electrical_dst(e);
  input e; electrical e;
  initial #10 $display("%M: %f", V(e));
endmodule

// Module ams_wreal_src.vams
`timescale 10ns / 10ps
//`include "disciplines.vams"
module ams_wreal_src(w);
  output w; wreal w;
  assign w = 2.5;
endmodule

 Compile :

irun -timescale 1ns/1ps -discipline logic -ieinfo ieinfo.txt top.sv ams_electrical_src.vams ams_electrical_dst.vams ams_wreal_src.vams

Errors:

 Discipline resolution Pass...
ams_electrical_src e_s1(r);
                        |
ncelab: *E,CUVNCM (./top.sv,7|24): No connection module found:Need a wreal input port of continuous discipline electrical, and an output port of discrete discipline logic, at instance top.e_s1.
ams_electrical_dst e_d1(xr);
                         |
ncelab: *E,CUVNCM (./top.sv,10|25): No connection module found:Need a wreal input port of discrete discipline logic, and an output port of continuous discipline electrical, at instance top.e_d1.
irun: *E,ELBERR: Error during elaboration (status 1), exiting.

Tool: IUS 10.029

Questions:

1. Does IUS 10.029 support automatic insertion of connect modules as mentioned in the EE times article above?

2. I tried explicitly to use -setdiscipline to set the net "e" to electrical but to no avail

Any pointers/help to resolve this would be highly appreciated. I am planning on using SVA's in the test bench to monitor electrical signals from the analog blocks and hence the help would be highly appreciated. Thx

Hi , 

     I am trying to implement register backdoor access with user defined register backdoor by extending uvm_reg_backdoor.

        class peri_reg_backdoor extends uvm_reg_backdoor

            virtual task write(uvm_reg_item rw);

      $root.top.DUT.reg = 8'h41;

            endtask  

        endclass 

      when i  am compile this code it is showing error

      illegal location for a hierarchical name (in a package). 

      I want to know what is the overcome for this issue in IUS.

Thanks in advance

sagar 

 Hi all,

   i am getting stuck on simulating systemverilog code in cadence... DPI related systemverilog code is running under some other tool I need to run that code in cadence.  

   I compile systemverilog[*.sv] and *.CPP file using following command.

system verilog :

     ncverilog +define+$testcase+$mode +sv -f compile_list.f +ncdpiheader+dpi.h +elaborate +ncelabargs+-messages

     =>dpi.h is created...

 CPP:

     g++ -g -march=x86-64 -Wall -O2 -fPIC -I../cpp -include../dpi.h -I/`ncroot`/tools/inca/include -c $(sources_cpp) -DCADENCE

     g++ -march=x86-64 -shared *.o -o $(TARGET)

 $(TARGET) => shared library file *.so

Simulation:

    in simulation i need to include that above shared library *.so

    what is the command line  argument for simulate

     => ncsim +sv_lib=../*.so +access+r+w +ncsimargs+"-sv_root ./" .?....

Kindly help me for this issue...

Thanks,

selvavinayakam.na

While running an IFV assertion check, the trace and trigger are showing the status "Pass" whereas the result is shown as "Fail".

 Please tell me where the issue could be?

hi, can any one help me to find the problem in my project.

i am doing asic implementation of reed solomon encoder, in that while doing rc timing extraction i am not getting the timing delay value...

can any one tell where i have gone wrong...

thanku...

 Hi,

I am getting the following specman related error. Modified the $PATH variable accordingly but of no use.

Any ideas from anyone?

Thanks,

Naveen

Here is the run.log file:

************************************

SEED=30561
Copying /MENTOR/install/modelsim_se_10.0c_2011_08/modeltech/linux/../modelsim.ini to modelsim.ini
Modifying modelsim.ini
Modifying modelsim.ini
Reading /MENTOR/install/modelsim_se_10.0c_2011_08/modeltech/tcl/vsim/pref.tcl

# 10.0c

# vsim +OVM_TESTNAME=test +define+QUESTA +MSEQ_COUNT=2 +define+ENET_TENGKR -do {coverage save -onexit ./cov/test.ucdb;do /xx/xx/waves_full.do; sn test; set SolveArrayResizeMax 10000; run -all; exit} -dpioutoftheblue 1 -gblso /CADENCE/VIPCAT11.30.013_OVM/tools.lnx86/denali_64bit/libmtipli.so -l ./logs/test.log -c -pli /CADENCE/VIPCAT11.30.013_OVM/tools.lnx86/denali_64bit/libmtipli.so -pli /CADENCE/VIPCAT11.30.013_OVM/tools.lnx86/specman/lib/64bit/libmti_sv_sn_boot.so -suppress 3009 -t 1ps -novopt -sv_lib /CADENCE/VIPCAT11.30.013_OVM/tools.lnx86/specman/lib/64bit/libmti_sv_sn_boot -sv_lib /xx/xx/denaliEnetSvIf specman specman_wave top_level_top
*** Error: Specman is unable to execute sn_root. Add <Specman installation directory>/bin to the beginning of your PATH.
# Loading /var/tmp/xxx_dpi_28019/linux_x86_64_gcc-4.1.2/export_tramp.so
# Loading /CADENCE/VIPCAT11.30.013_OVM/tools.lnx86/denali_64bit/libmtipli.so
# Loading /CADENCE/VIPCAT11.30.013_OVM/tools.lnx86/specman/lib/64bit/libmti_sv_sn_boot.so
 ************************************

I am using -profile to investigate why my simulation is so slow, and I found the warning:

ncsim: *W,FLSTRT

the explanation of it is: The assertion is spending a significant amount of time starting new
        attempts that immediately terminate.  In most assertions, such activity
        can be minimized by optimizations in ncsim; something about this
        assertion is preventing those optimizations from taking effect. 

I want to know what prevent the optimization, how can I fix it?

 My assertion is fairly simple as below:

 property check_conflict;
      @(posedge clk) ((a && b && !c) ##1 (d && c)) |-> ##[0:2]  S;
   endproperty
   conflict:assert property (disable iff (!rst_an) check_conflict)
         else `uvm_error("ERROR",$psprintf("conflict at %0t \n",$time))

 Could anyone help? Really appreciated.

Hi 

I am new to standard cell, during reading the .lib report i found out there is dont_use and dont_touch on some cell.

can any one let me know what do they mean

thanks 

HI

How do i call/access the parameter which is defined inside a verilog module and then modify the values of the parameter so that the module behaves differently each time I run it.

I am trying to control the parameter of a module through a TCL testcase

Thanks

Hi,

   for Initial Stage I just create Dummy Wrapper in UVM-SV for Checking purpose...

Below is my Dummy file test.sv 

This file contain - sequence_item,driver,monitor,environement,top_tb,dut and interface...

*** => important things are in Bold letter...

`include "uvm_macros.svh"

interface dut_if;
  logic clk;
  logic [7:0] addr;
  logic [7:0] data;
endinterface

module dut(dut_if m_dut_if);
  import uvm_pkg::*;
  always@(posedge m_dut_if.clk)
  begin
    `uvm_info("", $sformatf("POSEDGE: DUT received addr=%d, data=%d",m_dut_if.addr,m_dut_if.data),UVM_MEDIUM)
  end
  always@(negedge m_dut_if.clk)
  begin
    `uvm_info("", $sformatf("NEGEDGE: DUT received addr=%d, data=%d",m_dut_if.addr,m_dut_if.data),UVM_MEDIUM)
  end
endmodule

package hello_pkg;

  import uvm_pkg::*;

  class hello_sequence_item extends uvm_sequence_item;
    `uvm_object_utils(hello_sequence_item)
    rand int addr;
    rand int data;

    constraint c_addr { addr >= 0; addr < 256; }
    constraint c_data { data >= 0; data < 256; }

    function new (string name = "");
      super.new(name);
    endfunction

    function string convert2string;
      return $sformatf("addr=%0d, data=%0d",addr,data);
    endfunction

    function void do_copy(uvm_object rhs);
      hello_sequence_item tx;
      $cast(tx, rhs);
      addr = tx.addr;
      data = tx.data;
    endfunction

    function bit do_compare(uvm_object rhs, uvm_comparer comparer);
      hello_sequence_item tx;
      bit status = 1;
      $cast(tx, rhs);
      status &= (addr == tx.addr);
      status &= (data == tx.data);
      return status;
    endfunction
 
  endclass: hello_sequence_item

  typedef uvm_sequencer #(hello_sequence_item) hello_sequencer;

  class hello_sequence extends uvm_sequence #(hello_sequence_item);
    `uvm_object_utils(hello_sequence)
    hello_sequence_item item_h;
    function new (string name = "");
      super.new(name);
    endfunction

    task body;
      if (starting_phase != null)
        starting_phase.raise_objection(this);

      repeat(8)
      begin
        item_h = hello_sequence_item::type_id::create("item_h");
        start_item(item_h);
        if( !item_h.randomize() )
          `uvm_error("", "Randomize failed")
        finish_item(item_h);
      end
     
      if (starting_phase != null)
        starting_phase.drop_objection(this);
    endtask: body

  endclass: hello_sequence

  class hello_driver extends uvm_driver #(hello_sequence_item);
    `uvm_component_utils(hello_driver)
    virtual dut_if m_dut_if;
   
    function new(string name,uvm_component parent);
      super.new(name,parent);
    endfunction

    function void build_phase(uvm_phase phase);
      if( !uvm_config_db #(virtual dut_if)::get(this, "", "dut_if", m_dut_if))
        //`uvm_error("CONFIG", "uvm_config_db::get failed")
        `uvm_fatal("CONFIG",{"config must be set for : ",get_full_name(),".m_dut_if"});
    endfunction

    task run_phase(uvm_phase phase);
      forever
      begin
        seq_item_port.get_next_item(req);

        // Wiggle pins of DUT
        @(posedge m_dut_if.clk);
        m_dut_if.addr = req.addr;
        m_dut_if.data = req.data;
        `uvm_info("", $sformatf("DRIVER POSEDGE addr=%d, data=%d",m_dut_if.addr,m_dut_if.data),UVM_MEDIUM)
        @(negedge m_dut_if.clk);
        m_dut_if.addr = req.addr;
        m_dut_if.data = req.data;
        `uvm_info("", $sformatf("DRIVER NEGEDGE addr=%d, data=%d",m_dut_if.addr,m_dut_if.data),UVM_MEDIUM)
       
        seq_item_port.item_done();
      end
    endtask

  endclass: hello_driver

  class hello_monitor extends uvm_monitor;
    `uvm_component_utils(hello_monitor)

    int mon_addr;
    int mon_data;
    virtual dut_if m_dut_if;
   
    function new(string name,uvm_component parent);
      super.new(name,parent);
    endfunction

    function void build_phase(uvm_phase phase);
      if( !uvm_config_db #(virtual dut_if)::get(this, "", "dut_if", m_dut_if))
        `uvm_error("", "uvm_config_db::get failed")
    endfunction

    task run_phase(uvm_phase phase);
      forever
      begin
        @(negedge m_dut_if.clk);
        mon_addr=m_dut_if.addr;
        mon_data=m_dut_if.data;
        `uvm_info("", $sformatf("MONITOR NEGEDGE addr=%d, data=%d",mon_addr,mon_data),UVM_MEDIUM)
        @(posedge m_dut_if.clk);
        mon_addr=m_dut_if.addr;
        mon_data=m_dut_if.data;
        `uvm_info("", $sformatf("MONITOR POSEDGE addr=%d, data=%d",mon_addr,mon_data),UVM_MEDIUM)
        m();
      end
    endtask

    task m();
      `uvm_info(get_type_name(), "I am here", UVM_MEDIUM)
    endtask

  endclass: hello_monitor


  class hello_env extends uvm_env;
    `uvm_component_utils(hello_env)
  
    hello_driver driver;
    hello_sequencer sequencer;
    hello_monitor monitor;

    function new(string name,uvm_component parent);
      super.new(name,parent);
    endfunction

    function void build_phase(uvm_phase phase);
      sequencer = hello_sequencer::type_id::create("sequencer",this);
      driver    = hello_driver::type_id::create("driver",this);
      monitor   = hello_monitor::type_id::create("monitor",this);
    endfunction
 
    function void connect_phase(uvm_phase phase);
      driver.seq_item_port.connect( sequencer.seq_item_export );
    endfunction

  endclass: hello_env

  class hello_test extends uvm_test;
    `uvm_component_utils(hello_test)
    hello_env my_env;
   
    function new(string name,uvm_component parent);
      super.new(name,parent);
    endfunction

    function void build_phase(uvm_phase phase);
      my_env=hello_env::type_id::create("my_env",this);
    endfunction

    task run_phase(uvm_phase phase);
      hello_sequence seq;
      seq=hello_sequence::type_id::create("seq");
      `uvm_info("", "Hello World_0", UVM_MEDIUM)
      if( !seq.randomize() )
        `uvm_error("", "Randomize failed")
      seq.starting_phase = phase;
      seq.start(my_env.sequencer);
      `uvm_info("", "Hello World", UVM_MEDIUM)
    endtask
  endclass: hello_test

endpackage: hello_pkg

module top;
  import uvm_pkg::*;
  import ml_uvm::*;    => ///For multi-Language interaction i am just import multi-language

import hello_pkg::*;

  dut_if dut_if1 ();
  dut    dut_m ( .m_dut_if(dut_if1) );

  initial
  begin
    dut_if1.clk = 0;
    forever #5 dut_if1.clk = ~dut_if1.clk;
  end
 
  initial
    begin
      uvm_config_db #(virtual dut_if)::set(null, "*", "dut_if", dut_if1);
      //uvm_top.finish_on_completion = 1;
      run_test("hello_test");
  end
endmodule
 

 if I run above test.sv in cadence simualtor with following command #! /bin/sh -f
IUS_HOME=`ncroot`
irun -access rw \
-uvmhome ${IUS_HOME}/tools/uvm-1.1 \
-uvmtop sv:hello_env \
test.sv

I am getting below error,

   UVM_FATAL test.sv(98) @ 0: hello_env.driver [CONFIG] config must be set for : hello_env.driver.m_dut_if

--- UVM Report catcher Summary ---

  anybody Guide me to Resolve this issue...

Thanks,

selvavinayakam.na

 Hi all

I am using HAL for e linting and facing a problem with filtering source file for linting.

I am using the a design_info.txt file method to filter files that i don't want to lint.

however, this method works only for the built-in rules and doesn't affect the user defined rules (rules created by me).

Is there a way to fix this behavior of the HAL linter ?   i saw that there is a way to use a callback method for HAL messages, is this the only way to deal with this problem ?

Thanks in advance.

E.M. 

Hi Iam using IFV 12.20.007.Iam trying to pass constraint for a design,What is the procedure to give give constraint such if statement.

Ex:  i have condition to be satisfied iam using if statement for that if(my condition are true) then constraint should be given 

Thanks

Bharath