Hi,
I need to re-use the constants and record type variables in system verilog which are defined in vhdl DUT (in a separate package file). I could not find the idle way to do this task except rewriting the constants in systemverilog again with some manual work. I tried with import statement but didnt work. I was not sure whether i need to add any extra command line arguments to do this. Could any one please shed a light on this?
Thanks for your time.
Regards,
raja
I'm looking for a way to read a file containing (HEX) numbers.
For each file I read, the width of the data is different (can be more than 32/64/128 bits).
So I'm looking for a way to convert the string I read from the file to a list of bit variable.
In order to make it easy, let say I know the size of the bits list (the data width) in advance.
Any ideas?
The format for the xls to enter connectivity isn't very clear in the user manual. Can anyone give me a sample?
Thanks.
Hello!
I'm trying to make this band-gap ref. circuit to work but, up to now, i haven't reached the right result.
I've already checked the circuit, but i couldn't find any misconnections on it.
Can you guys please help me debugging it? I'm workin on it for about 2 week and no success... this is really stressing me out.
Thx for your patience.
Cheers,
Fávero
Hi
I finished running a set of simulation tests with coverage, and now I am trying to merge the coverage, but I got the following error. I am able to load individual test, but I can not merge all of them into one. Please let me know what I have to do. Thanks!
iccr> merge * -output all
iccr: *W,MGURTS: The merge command could not resolve the test specification "./cov_work/scope/*". Verify the existence of complete test specification for the specified test.
iccr: *E,MGLSDB: Merge operation could not proceed because of insufficient number of unique tests.
Hi,
I'm using the irun command. I want to pass an option -binding to the ncelab. How do I do this?
Thanks.
Hi,
Is there a way to bind vhdl outputs with my SV checker module input ports? And also how do i access vhdl ports from my sv testbench?
Thanks,Rajay
Hey,
The automatic assertions take a very large time to run as my design is huge.
Could anyone tell me which is the best engine to use so that I can fasten this process?
Thanks.
Hey,
I entered connectivity information onto an xls and generated assertions on IFV. These take a very long time to run. If I write similar assertions myself, it runs faster. The only difference between them is mine have @ and is checked only during transitions.
Example:
Generated by IFV :
Assertion_0 : assert property (
(A && B) |-> (C === D);
Written by me:
property assert_0;
@(`A)
(A && B) |-> (C===D);
endproperty
Assertion_0: assert property (assert_0);
Why is this so? Can I improve the run time for automatically generated assertions?
I've used the assertion -add -automatic command.
But this doesn't add any assertions, but gives a warning saying: Session does not have any assertion.
It runs user-defined assertions. Also, when the command is run with this, it says 0 assertions added.
How do I rectify this?
Hi,
Iam doing formal verification om certain block and iam having some of the display statement in source module.WIll those display statements displayed when i do simulation using IFV.
Ex:- iam having $display statement which is not getting generated in the log what could be the reason.
Hi,
I need to view the variables used inside a function in simvision waveform viewer.
How to add a probe to view these variables in the viewer?
Thanks,
Venkat
Hi
Iam doing formal verification,Iam getting so many signals unitialized.Iam not understanding which signals we should initialize.How to know which signals we should initialize in a module.
Hi Everyone!
Im new in this whole SV Assertions world, and Im having some troubles trying to define a "property library". Basically, what I want to do, is to have all my properties definitions in a separate file, and to have the assert property ... setences in a separate file, in order to use the one property in more than one assertion file.The problem is thatI cant find a way to acces to the property definition from the assertion file.
Is there any way to achieve this? Because all the documentation I have seen, have the property declaration and the assert directive in the same file.
Thank You,
Paulo
I'm looking for a way to read a file containing (HEX) numbers.
For each file I read, the width of the data is different (can be more than 32/64/128 bits).
So I'm looking for a way to convert the string I read from the file to a list of bit variable.
In order to make it easy, let say I know the size of the bits list (the data width) in advance.
Any ideas?
Hi
Iam having some of the assertions result as block.What do you mean by block and how to make those assertions passing or failing.
Thanks
Bharath
Hi,
We need to create system C wrapper over System verilog[SV Environment Database]. if any body have idea please share it...
Note:
SystemVerilog Database which is in SCEMI MODEL....
Thanks,
Ramanathan.CT
In my code simulation ,it must be have boot action at the beginning of process. I want to skip it to save time, so i use snapshot funtion.
But my test pattern is putting on TOP module. The snapshot file is launch older test pattern even i have replace the test pattern.
Can I use the snapshot funtion to achieve my purpose?
Thanks
Hello,
Can anyone tell what the advantages of the Super Linting features in over the SpyGlass Linting?
Thanks.
Under the old 3-step process (ncvlog+ncelab+ncsim), I could compile the testbench once. Then call ncsim multiple times to run the sim again(without recompiling.)
How do I do that with irun? What are the proper command-line switches?
