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March 3, 2013, 5:45 am
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 Ethan longs to escape his small Southern town. He meets a mysterious new girl, Lena. Together, they uncover dark secrets about their respective families, their history and their town.

Watch Beautiful Creatures Online Free Streaming Movie In HD


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Watch Beautiful Creatures Online Free Full Streaming (2013) Movie Obviously these people fall madly in love : yet relationship just isn’t merely white or black when your courting a Caster, with the girl odd loved ones and also murderous mom in order to contend with, would they make it through or even will certainly Lena’s fast-approaching sixteenth birthday celebration split them aside for good?

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IMC Exclusion Problem

February 10, 2013, 8:46 pm
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Hey all,

 I am using IMC for my coverage .The problem is the tool automaticaly excludes some block coverage or expressions from the coverage.It shows "Exclusion Rule type : simulation time".Can someone explain what does Exclusion Rule typr mean and how do I remove it so that I can cover all blocks and expression in the Coverage.

 Thank you.

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VCS to IRUN Conversion Error, UVM-1.1 System Verilog

February 14, 2013, 9:57 pm
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Hi,

   I am using INCISIV 11.1 to compile a project which works perfectly on VCS, However I get the following errors on cadence using the irun command .

ncvlog: *E, CLSSLV Class reference illegal in this reference on line :

 data_in[0] <= link_if.cbd.link_tx_serdes_data_0

and ncvlog: *E, DYNNBA Reference to whole or element of dynamic array/fixed array of dynamic array are illegal in this context

data_in is declared as a protected logic [`OSI_WD_WIDTH-1:0] data_in [ ] and initialized to size 16.  link_tx_serdes_data_0 is declared as logic [`OSI_SERDES_WIDTH-1:0] in an interface. link_tx_serdes_data_0 is declared as an input in clocking block cbd.

The data_in is also registered as a uvm_component:

.....

`uvm_field_array_int(data_in,UVM_ALL_ON)

 

All required files have been compiled prior to compiling this file. And the whole project works perfectly on VCS. 

 

Maisum.

 

 

 

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ncsim: *F,INTERR: INTERNAL ERROR

December 22, 2008, 1:17 am
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 Hi,

 Test : DRAM write and read up to 2GB . 

 Simulation fails with the following error. Can anbody please help me out?

ncsim(64): 06.20-p001: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
ncsim: *F,INTERR: INTERNAL ERROR
Observed simulation time : 0 FS + 0
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
  TOOL: ncsim(64)       06.20-p001
  HOSTNAME: XIDCTEA1
  OPERATING SYSTEM: Linux 2.6.9-55.ELsmp #1 SMP Fri Apr 20 16:36:54 EDT 2007 x86_64
  MESSAGE: System virtual memory limit exceeded (0x100000d8/0x2b6bba4010)
-----------------------------------------------------------------

 

 

Note : I had checked the enough  physical memory and also virutaul memory available for the host.

Thanks,

Sankara

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Why do I get an error when I try to generate (any) system Verilog module?

February 18, 2013, 1:55 am
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If I try to make a new cell view of type system verilog from the library manager GUI I systematically get this error (the content of the module does not matter):

F,AMSASV: The -ams and -sv options cannot be used together.

Which means that I cannot get a symbol and so on...

I checked all my options and I don't see why the -ams option is kicking in.

Any help woudl be greatly appreciated!

Thanks,

Giorgia

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Is it possible to make a system verilog module from the library manager GUI?

February 18, 2013, 1:56 am
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If I try to make a new cell view of type system verilog from the library manager GUI I systematically get this error (the content of the module does not matter):

F,AMSASV: The -ams and -sv options cannot be used together.

Which means that I cannot get a symbol and so on...

I checked all my options and I don't see why the -ams option is kicking in.

Any help woudl be greatly appreciated!

Thanks,

Giorgia

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Failure of liveness property

February 20, 2013, 5:52 am
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Hi everybody

I'm trying to verify the following property:
-- psl assert_p1: assert always ( (CS = st_idle) -> next eventually! ((CS = st_get_ack) or (CS = st_set_ack)) );

The section "Waveforms for Liveness Assertions" of chapter 9 on the document Formal Verifier User Guide says: "A failed liveness assertion has an associated counter-example in which there is an infinitely repeating sequence of non-satisfying states for the assertion." And this is exactly what the problem is. The property fails and the counter-example has a LoopMarker. I suppose I have to force IFV to verify for more time?

The DUT is a state machine implementation in which CS is a user-defined type signal representing the current state and st_idle, st_get_ack, st_set_ack, etc are states of the state machine. st_idle has a transition for itself until it matches a value for three different signals. The VHDL code of this behaviour is the following:

when st_idle =>

    if ready_i = '1' and busy_s = '0' then
        NS      <= st_get_ack;
    
    elsif ready_frame_i = '1' then
        NS      <= st_set_ack;

    else
        NS      <= st_idle;The property above checks if  

 
It's interesting that a property checking if states st_set_ack and st_get_ack are never achieved and failed as well:
-- psl assert_pn1: assert never ( (CS = st_get_ack) or (CS = st_set_ack) ); 
  
What can I do?
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re : parameterized sequences & property blocks in simvision

February 22, 2013, 1:42 am
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HI,

    I have a strange problem with my simvision (version 11.10.-s66) that i have  written 2 assertions

      1) with parameterized sequnces and property 

      2) normal assertion 

     for some logic which you can find in the below code , but in the simvision the assertions finished at different timings , the one parameterized finished one clock pulse later than expected and the normal assertion finished properly. So can any one tell me whether it is tool issue ???


initial
begin
    clk = 1'b0; in1 = 4'd0; flag = 1'b0; out1 = 4'd0;
    repeat(2) @(negedge clk); in1 = 3'd2; flag = 1'b1;
    repeat(1) @(negedge clk); flag = 1'b0; out1 = 3'd3;

    repeat(5) @(negedge clk); $finish;
end

property p1;
    @(posedge clk)
        ( (in1 == 3'd2) && $rose(flag) ##1 $fell(flag)) |-> (out1 == 3'd3);
endproperty

    chk1 : assert property(p1) $display("Working Good");
            else $display("Not Working");

sequence s1(a);
    $rose(a) ##1 $fell(a);
endsequence


property p2(a1,b,c);
    @(posedge clk)
    ( (b == 3'd2) and s1(a1)) |-> ( c == 3'd3 ) ;
endproperty

    chk2 : assert property(p2(flag,in1,out1)) $display("Working Good");
            else $display("Not Working");

 

Find the attachment for the picture containing assertions in the simvision

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SVA library in Cadence INCISIV

February 25, 2013, 10:23 pm
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Hi,

I am migrating my project from Synopsys VCS to Cadence INCISIV. My project uses SVA library Cadence's library ial can not be used in this case. I get the following error when I compile the SVA library (VCS) in Cadence :

ncvlog: *E,ILLSVF (../design/asserts/sva_cg/assert_dual_clk_fifo.v,541|39): Illegal use of sampled value function outside concurrent assertions and procedural blocks.
assign enq = $sampled(i_enq);
|
If i dont use the SVA library. The assertion properties are not found even if i use Cadence ial library instead.

Is there someway to compile using VCS SVA for the assertions in Cadence ? I am using the irun command.

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Engineering Fix

March 4, 2013, 12:50 am
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Hi I have been given an Engineering fix for a problem in formal tool. The IT suppor has installed it but I am not sure how to use it.

Usually the tool is used by seting SOCV_KIT_HOME and sourcing env.csh

But I am not finding any such file at the folder kits/VerificationKit

 I will be thankful if someone can give early solution to this.

Regards,

Avni

 

Sorry to post this issue here. I am not sure on which foum this should be posted. 

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Retrieve Flat Net Wire Properties using TCL

March 4, 2013, 5:42 pm
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Using the script example in section 3.2.20 of the OrCAD Capture TCL/TK Extensions Application Notes I was able to pull the net names. To get the other information I need (user properties, port information, page location of port, etc.) I have tried using the DboFlatNetNetsIter and DboFlatNetWiresIter to get the DboNet and DboWire classes which I would then use to get the other information (I have been able to get all the information via iterating through schematic > pages > wires). However, when I call the NextWire or NextNet my script crashes OrCAD. The classes instances calling these methods are not null.

 (continued from 3.2.20 after $lFlatNet GetName $lName)

set lFlatNetWiresIter [$lFlatNet NewWiresIter $lStatus]
# check lFlatNetWiresIter and lFlatNet for null
set lFlatNetWire [$lFlatNetWiresIter NextWire $lStatus]

 Has anyone had success using the DboFlatNetWiresIter_NextWire or DboFlatNetNetsIter_NextWire?

 

 

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Bidirectional has() and count() List Pseudo-Methods

March 5, 2013, 1:13 am
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Hi.

As of the 11.1 release, the list.has() and list.count() list pseudo-methods can be treated as bidirectional constraint operators.

In 11.1, list.has() and list.count() are solved unidirectionally by default. To ensure that these pseudo-methods are solved as bidirectional expressions, set the config gen -bidir_list_pseudo_methods configuration flag.

This works but in the manual it says that this can be also done from the Specman e code by extending setup() of sys to contain:

set_config(gen, bidir_list_pseudo_method, ALL);

But this latter option does not work.

Can anyone offer some help on how to do this from the Specman e code?

I also tried using specman("config gen -bidir_list_pseudo_methods=ALL") and it did not set this config option.

Thanks in advance!

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Issue in merging two coverage runs with different checksums in IMC.

March 7, 2013, 9:24 am
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Hi all,

     I am trying to merge two different coverage runs with different checksum. It is not getting merged. I am getting messages like below.

    Block coverage not merged - Checksum differs.
    Expression coverage not merged - Checksum differs.
    Instance not found in the target model. Use the "merge_config" command (prior to the "merge" command) to map the source instance/type to the target instance/type

Is it possible to merge coverage runs with different checksums. Please let me how to merge the coverage in this case.

Thanks in advance,

Clair..

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UVM_REG backdoor access

March 7, 2013, 9:26 pm
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Hi , 

     I am trying to implement register backdoor access with user defined register backdoor by extending uvm_reg_backdoor.

 

        class peri_reg_backdoor extends uvm_reg_backdoor

            virtual task write(uvm_reg_item rw);

      $root.top.DUT.reg = 8'h41;

            endtask  

        endclass 

      when i  am compile this code it is showing error

      illegal location for a hierarchical name (in a package). 

      I want to know what is the overcome for this issue in IUS.

 

Thanks in advance

sagar 


 

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TCL based assertion for connectivity check

March 8, 2013, 1:49 am
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Hi,

 I am using ncsim and i wish to check connectivity between two nets in RTL/netlist using tcl. I remember there being someway where using tcl input file i could specify two nets which could be tested for connectivity.

ex:
 -src net1  -dst net2

on a change of net1 check net2 value is equal to net1 value. kind of an tcl assertion

I dont remember the syntax. kindly help

thnaks!
Harsha

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