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How to effectively browse verilog source in Cadence

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Hi,

I know simvision can do source/load driver tracing but I believe it is more aimed at actual value tracing more than "browsing" through the code. I.e. I am looking for a Verdi style tracing, where it is easy to stop at module boundaries, the hierarchical panel on the left tells me where I am, etc. I find it really useful in seeing the bigger picture with regards as architecture, interconnections b/w modules and so on. In Simvision I just get lost when moving across boundaries, I could never find a way to make it work the way Verdi does. I am not sure I am using the right tool for the job?

Thanks


How to effectively browse verilog source in Cadence

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Hi,

I know simvision can trace do source/load driver tracing but I believe it is more aimed at actual value tracing more than "browsing" through the code. I.e. I am looking for a Verdi style tracing, where it is easy to stop at module boundaries, the hierarchical panel on the left tells me where I am, etc. I find it really useful in seeing the bigger picture with regards as architecture, interconnections b/w modules and so on. In Simvision I just get lost when moving across boundaries, I could never find a way to make it work the way Verdi does. I am not sure I am using the right tool for the job?

Thanks

How to make defparam disappear in netlist generated by NC-verilog in Cadence

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Hi all,

I am looking the option so that the defparam is not shown in the netlist generated by NC-verilog in Cadence.

This is one example of the netlist with defparam:

ainv_lvt I1 (net01, net02, vdda, gnda);

defparam

              I1.delay = 0;

 

Thanks.

Dumping only last 1ms log file information in irun/xrun

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Hi,

To manage log file size. I would like to dump out the log information for only last 1ms. Is there a way to do that in irun/xrun tcl input script?

There are are lot of test cases and the time duration for  each test case is different , so there is no way of knowing the duration of the test before the simulation begins.

Thanks,

$xm_deposit in gate level simulation

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Hello,

i tried to deposit a value inside a register using this code:

$xm_deposit("tb_chip_top_s222.dut_u.i_digtoppad.i_dig_top_pads.i_dig_top.i_volt_cfg_regs.i_cfg_3_secded.\\secded_data_r_reg[0] .Q", $sformatf("%b", cfg_3_secded_register_value[0]));

This works in rtl simulation but i have some issues in gate level simulation where the deposit seems to behave like a force ( i see the D signal of the flip flop equal to 1 but it is not sampled after the posedge of the clock, maybe beacuse of the deposit on Q)

Any suggestions?

Thanks

VPlan Report- links for each test

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Hi all,

I would like to generate a vplan report in order to have an html link for each entity of the plan.so people that want to check if the requirment has been covered can click on the link and see the results relatives to that req..Do you know if it is possible?

Thanks,

Max

Voltus-Fi vpserro layers displayed

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Hello everyone,

I am currently adapting Voltus-Fi to the design flow (UMC180 technology).

The EM/IR analysis through ADE-L seems to work (judging by changing the output plots).

But displaying Results > EM/IR Data > Layout Analysis with choosing IR-drops for the nets (say AVDD) fails, since vpserro layers are not displayed on the layout view (although these layers are visible in the Palette tab and in the IR/EM Results window min and max values are as well specified and differs through various nets).

Have you any ideas how to deal with this problem?

Regards,
Artur

using eManager to read regression files but failed.

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when i tried using eManager to read regression files but failed, so no data is available when click vplan button for verification plan map and code coverage analysis using IMC.

eManager's log is attached below. can anyone who had any experience on this help? thanks so much.

*** Warning: VM_UCM_FILE_READ_FAILED: Failed to read coverage model file /user/hxzh.tmp/20190513/nor_regression.hxzh.19_05_27_10_23_55_8052/testcase_model_28a5ee8a-8061-11e9-b383-bb4d3052dabc_nor_regression_default.ucm. Model skipped.

To change the severity, type:
set notify -severity=<new-severity-level> VM_UCM_FILE_READ_FAILED
To see possible severity levels use 'set notify -help'


*** Warning: VM_UCM_FILE_READ_FAILED: Failed to read coverage model file /user/hxzh.tmp/20190513/nor_regression.hxzh.19_05_27_10_23_55_8052/model_dir/icc_73072a11_5c7615b8.ucm. Model skipped.

To change the severity, type:
set notify -severity=<new-severity-level> VM_UCM_FILE_READ_FAILED
To see possible severity levels use 'set notify -help'


NCLaunch VHDL compiler *F,DLUNNE error

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I'm trying to compile a VHDL code via NCLaunch. However, I keep getting the following error on the console

*F,DLUNNE: Can't find STANDARD at /vlsi/apps/cadence/ius/8.2HF015/tools/inca/files/STD.

There exists a folder named "standard" under the given path. There is no error in the VHDL code, either. During the cds.lib creation, I chose to add IEEE Pure libraries.

I can compile and elaborate Verilog code no problem, but VHDL compiler just doesn't work. I'm not sure what's happening. Please let me know if you need more information. Any help is appreciated.

Export a Breakpoint

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Hi all,

I was running a simulation with Xcelium in Simvision and I save few breakpoints.

I would like now to run another simulation (so from a different console) and loading one of the breakpoints of another simulation 

Is this possible? 

I try with the File -> Save Command Script and then sourcing the restore file but it is taking a lot of time

NC-Verilog user manual

Load several shared object

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Hello everyone,

I have a question about DPI-C , i know i can load a shared object using irun, even if you need to call it libdpi.so to load it . But I want to load several shared object and not only using the default "libdpi.so" ? because i have several shared object corresponding to a function, and i want to call several function from different shared object ... 

Is it possible to do this ?

thank you by advance,

Sincerely,

[IMC] Toggle coverage report

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Hi,

Is it possible to consider only 0->1 or 1->0 transition condition in toggle coverage report ?

I mean that I want to consider that a net is full covered if one of this transition is respected but not only if I have the both.

Thanks.

Nabil

Efficient way to create vpi handles and callbacks

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Hello Everyone,

Currently I am using following VPI calls to create handles and callbacks to my design hierarchal signals.

vpiHandle handle = vpi_handle_by_name( , );

cb_handle = vpi_register_cb(&cb_data);

Issue is that, for "n" number of nodes I need to call these commands "n" times and as the number of signals increases this whole process becomes significantly time taking.

 Is there any more efficient and  faster way to create multiple handles/callbacks in one go. I need to create millions of such handles and call backs.

I will really appreciate any inputs on this.

Thanks,

VManager wrongly imports failed test as passed

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Hello,
I'm exploring VManager tool capabilities.

I launched a simulation with xrun, which terminates with a fatal error (`uvm_fatal actually).

Then I imported the flow session, through VManager -> Regression -> Collect Runs, linking the directory with ucm and ucd of just failed run.

VManager imports the test with following attributes:

Total Runs =1

#Passed =1

#Failed =0

What I'm missing here? It should be imported as failed test.

If I right click on flow name and choose Analyze All Runs, VManager brings me to Analysis tab and I can see only a PASSED tag in Runs subwindow.

Thank you for any help


-std=c++14 support for XCC compiler in Xtensa Xplorer

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Hello,

      I am trying to do some program with Vision P5 DSP. where I have to use some typecasting of class members and also to use templates that all are supported with the flag -std=c++14. But the xcc is throwing error that it is an unknown flag. I need to know whether the -std=c++14 flag is available in any new updates of the tool or any similar flags to -std=c++14 is available for the compiler. 

Thanks in advance,

Indrajith

Design library not defined while reading module with ncsim

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Hi supporters,

I got the following error while I run simulation with gate netlist using Cadence Incisive (v15.20):

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ncsim(64): 15.20-s076: (c) Copyright 1995-2019 Cadence Design Systems, Inc.
ncsim: *E,DLOALB: Design library 'tcbnxxx' not defined while reading module tcbnxxx.MAOxxx:bv (VST).
ncsim: *F,NOSIMU: Errors initializing simulation 'alu_tb' 

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xxx: standard library name.

My netlist design uses a cell "MAOxxx". I already included the library behavior model to compile using ncverilog, there is no error while compiling. But when I run with ncsim to execute the test, I got above error.

I tried to run with other vendors such as VCS or MTI, they worked.

 

Please help to understand the error.

Thanks.

Force cell equivalence between same-footprint and same-functionality hard-macros in Conformal LEC

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For a netlist vs. netlist LEC flow we have to solve the following problem:

- in the RTL code we replicate a large array of N x M all-identical hard-macros, let call those MACRO_A

- MACRO_A is pre-assembled in Innovus and contains digital parts and analog parts (bottom-up hierarchical flow)

- at top-level (full-chip) we instantiate this array of all-identical macros

- in the top-level place-and-route flow we perform ecoChangeCell to remaster the top row of this array with MACRO_B

- MACRO_B is just a copy of the original MACRO_A cell containing same pins position, same internal digital functionality and also same digital layout, only slight differences in one analog block inside the macro

- MACRO_A and MACRO_B have the same .lib file generated with the do_extract_model command at the end of the Innovus, they only differ in the name of the macro

- when performing post-synthesis netlist vs post-place-and-route we load .lib files of both macros in Conformal LEC

- the LEC flow fails because Conformal LEC sees only MACRO_A instantiated in the post-synthesis netlist and both MACRO_A and MACRO_B in the post-palce-and-route netlist

Since both digital functionality and STD cells layout are the same between MACRO_A and MACRO_B we don't want to keep track of this difference already at RTL stage, we just want to perform this ECO change in place-and-route and force Conformal to assume equivalence between MACRO_A and MACRO_B .

Basically what I'm searching for is something similar to the add_instance_equivalences Conformal command but that works between Golden and Revided designs on cell primitives/black-boxes .

Is this flow supported ?

Thanks in advance

Luca

Export sessions to csv in cadence vmanager tool

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Hi all..

I need to generate the regression report (of selected sessions) in the form of csv file in cadence vManager tool in Batch mode using batch mode commands. The command I used is -

vmanager -execcmd csv_export -sessions -filter "start_time:=6/17/19 10:49 PM" -out regr.csv > temp

But I have been getting the following error-

*E,CMDERR: Command line error: Unrecognized option: -sessions

Can someone please let me know what exactly is causing error here and help me with this?

Simvision Schematic Information

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Hi all,

I would like to understand if it is possible from Simvision to get the information regarding the view of a block. In principle using the Schematic Tracer Simvision is able to find the information about the config of that particular model, but I did not found a command for describing the nature of the module (for example if it is schematic or rtl or real model...)

Any functions that I can use for this purpose?

Many thanks

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