Hi all..
I wanted to know if it is possible to generate the regression reports(in the csv file format) by vManager tool of Cadence at regular intervals of time(say 30 min or 1hour) automatically? Also is it possible to generate these .csv reports as and when triggered from an external webpage?
Hello Everyone,
Currently I am using following VPI calls to create handles and callbacks to my design hierarchal signals.
vpiHandle handle = vpi_handle_by_name( , );
cb_handle = vpi_register_cb(&cb_data);
Issue is that, for "n" number of nodes I need to call these commands "n" times and as the number of signals increases this whole process becomes significantly time taking.
Is there any more efficient and faster way to create multiple handles/callbacks in one go. I need to create millions of such handles and call backs.
I will really appreciate any inputs on this.
Thanks,
Hi Cadence,
I got below issue at "analyze RTL" step in Jaspergold Connectivity Check App.
Is there any command option to solve it ?
[ERROR (VERI-1817)] ...: parameter initial value cannot be omitted in this mode of verilog
I use command :
analyze -sv -f {<RTL file list>}
My module definition code :
module <mudule name> #(
parameter a,
parameter b,
parameter c
)
(
input x,
input y,
output z
);
Thanks,
Nghia Nguyen
Hi,
I am trying to disable VHDL assert but I was not able to find the option used by xrun to do that.
Anyone can help ?
Thanks.
Nabil
PS: following an example of the code implemented and its message:
assert(now - timeADXC >= tAVAV)
report "(Address valid to next address valid time violation (tAVAV = 70/90 ns) !!)"
severity warning;
ASSERT/WARNING (time 8329528909571 FS) from process testbench.prom_NCS0_1:timingCheck_process (architecture work.m29w800d_msb:behavior)
(Address valid to next address valid time violation (tAVAV = 70/90 ns) !!)
Hi all..
I need to generate the regression report (of selected sessions) in the form of csv file in cadence vManager tool in Batch mode using batch mode commands. The command I used is -
vmanager -execcmd csv_export -sessions -filter "start_time:=6/17/19 10:49 PM" -out regr.csv > temp
But I have been getting the following error-
*E,CMDERR: Command line error: Unrecognized option: -sessions
Can someone please let me know what exactly is causing error here and help me with this?
Hello all,
I've just started creating a more robust test bench structure using classes. I've never tried to use classes in verification before and so I'm having some trouble understanding how to view them in Simvision.
I've created a simple testbench with various classes for running the tests. I can see the classes in Simvision waveform window but there is no data for them. I do have data for the DUT signals and the testbench seems to be working correctly.
Is there something I need to do to make sure the data for classes is recorded? I'm using the $shm_probe to create the database but I don't see a switch for collecting class data.
Thank you for any assistance. I'm pretty new to Simvision so I'm probably missing a lot.
Dylan
Hello Cadence team,
I have been using cadence PVS for some time and I have noticed that PVS has the ability to show syntactical errors in the rules files. Basically, we get a red box around the rule section in Techc&Rules tab. I am looking if this is also available as a separate checker? Such that I can use it without having to invoke PVS.
Regards
Suryansh Singh
Hi,
I 'm having a problem trying to read an input file on a testbench on Incisive.
I believe the problem is due to a wrong file path, but I tried to copy the file to several folder and none worked.
The line I'm using, which worked in other simulator is:
file input_file: text is in "test_in.txt";
On Irun command, I obtain the error:
file input_file: text is in "test_in.txt";
ncvhdl_p: *E,ILLPRI (../tb/tb_top.vhd, 112|35): expecting an expression or operand [7.1] [7.3].
Any idea what could be the problem?
Thank you!
Hi all,
I have the extracted view of a 32-bit adder in subthreshold. Is there any tool in cadence to check the yield of the circuit?
ThANKS,
Hi All,
I'm trying to understand checkpoint concept. When I found save and restart concept in cdnshelp, There is just describing about "$save" and "xrun -r "~~~".
and I found also the below link about save restart and it saves your time.
But I can't find any benefits from my experiment from save&restart article( I fully agree..the article)
Ok, So I'v got some experiment Here.
1. I declared $save and got the below result as I expected within the simple UVM code.
In UVM code...
$display("TEST1");
$display("TEST2");
$save("SAVE_TEST");
$display("TEST3");
$display("TEST4");
And I restart at "SAVE_TEST" point by xrun -r "SAVE_TEST", I've got the below log
xcelium> run
TEST3
TEST4
Ok, It's Good what I expected.(The concept of Save and Restore is simple: instead of re-initializing your simulation every time you want to run a test, only initialize it once. Then you can save the simulation as a “snapshot” and re-run it from that point to avoid hours of initialization times. It used to be inconvenient. I agree..)
2. But The Problem is that I can't restart with modified code. Let's see the below example.
I just modified TEST5 instead of "TEST3"
$display("TEST1");
$display("TEST2");
$save("SAVE_TEST");
$display("TEST5"); //$display("TEST3");
$display("TEST4");
and I rerun with xrun -r "SAVE_TEST", then I've got the same log
xcelium> run
TEST3
TEST4
There is no "TEST5". Actually I expected "TEST5" in the log.From here We know $save can't support partially modified code after $save.
Actually, through this, we can approach to our goal about saving developing time.
So I want to know Is there any possible way that instead of re-initializing our simulation every time we want to run a test, only initialize it once and keep developing(debugging) our code ?
If we do, Could you let me know the simple example?
Hi all..
I need to generate the regression report (of selected sessions) in the form of csv file in cadence vManager tool using batch mode commands. The command I used is -
"vmanager -exec cmnd", where cmnd is a file containing the command' csv_export -sessions -view All_Sessions -filter "start_time:> 6/17/19 10:49 PM" -out regr.csv '
But I have been getting the following error-
Error:Project Environment Selection is required by server,and must be set on this mode
Can anyone let me how to resolve this?
Currently I am trying to verify an RTL file which is created with Parameters and Generate statments. This module is made this way so that I can be used multiple projects and adapt to the parameters that it is passed from the top level. I wanted to know if the JasperGold platform has any way to verify the module with various parameters automatically, or If I manually have to set these paramerts and then verify.
Thank you.
Hi,
I've ran couple of tests for below RTL code. One with parameter COUNTER equal to 1 and another test with COUNTER equal to 0.
Now, I could not merge the coverage for both tests cases.
Command used for merging : merge cov_work/scope/* cov_work/scope_0/* -out all (in imc -batch)
Warning message : *W,WEMMO1: Module/Generate/NamedBlock 'generate_check.genblk1_T' not merged because it is not present in target run.
*W,WEMIN1: Instance 'gen_tb.DUT.genblk1' and its hierarchy not merged with target instance 'gen_tb.DUT.genblk1' and its hierarchy - Mismatch in type names - Primary: worklib.generate_check.genblk1_F Secondary: worklib.generate_check.genblk1_T.
Total items not merged : 2
module generate_counter(clock, reset, count);
input clock, reset ;
output reg[3:0] count ;
parameter COUNTER = 0;
generate
if (COUNTER == 1) begin
always@(posedge clock) begin
if (reset)
count <= 4'b0;
else
count <= count +1;
end
end
else begin
always@(posedge clock) begin
if (reset)
count <= 4'b0;
else
count <= count +2;
end
end
endgenerate
endmodule
Is there any way in imc to merge the coverage with both parameter values ?
Can someone please help me how to merge the coverage in such cases.
Thanks.
Yes, I know its not a supported platform, it should be.
Most of the companies I work with run Ubuntu. Does anyone have a list of steps/libraries that need to be installed to get Xcellium working on Ubuntu?
thanks, Andy@CommLogicDesign
Hi all,
I have the following scenario for writing assertion.
Signal 'A' rises two cycles after 'B' falling. The high period of 'A' is, 70 + (var_value) clock cycles.
I wrote two assertions to check this scenario;
1. property A_RISE;
@(posedge clk)
$fell(B) |-> ##2 $rose(A); //to check the dependency of A w.r.t B
endproperty
ASSERT_A_RISE : assert property(A_RISE);
2. property A_HIGH_PERIOD;
@(posedge clk)
$rose(A) |-> A[*70] ##1 A[*var_value] ##1 !A; //to check the high period of A
endproperty
ASSERT_A_HIGH_PERIOD : assert property(A_HIGH_PERIOD);
Is there any better way to check both dependency and high period together?
How can we use variable cycle delays or sequence repetitions in assertion properties??
I have started to practice system verilog assertions recently only; Please provide me some guidelines to proceed with this.
Thanks
Hi dear all,
I am at a customer working on a SystemVerilog UVM - based verification environment…
without going (yet) too much deep in details I have that starting a simulation with a command line such as:
ifxxcelium execute -gui -- +UVM_TESTNAME=adas_err_monitor_test -svseed 5 -gpg '\"TLF30682_VER => 0\"' +uvm_set_config_int=uvm_test_top,test_nb,6 &
and starting it with
ifxxcelium execute -gui -- +UVM_TESTNAME=adas_err_monitor_test -gpg '\"TLF30682_VER => 0\"' +uvm_set_config_int=uvm_test_top,test_nb,6 &
and then giving in the tcl console:
set svseed 5; run <ENTER>
produces different results...
The ifxxcelium execute customer- specific- script passes what follows "--" simply to xrun (while it works on itself some of the switches before the "--" and then passes them to xrun)...
before going deep…. is a possible corner in the LRM to have different results if one uses the -svseed switch or the "set svseed <VALUE> " tcl command and then hits run ?
thx in advance!
Alex Ogheri
I am currently trying to do formal verification of safety mechanisms in JasperGold. However, part of the safety mechanism is first implemented in Firmware and later, based on this, safety flags are set/reset in HW.
Therefore, my question is that: Whether it is possible to do formal verification of firmware related functions in JasperGold(as in this case, it occurs in the cone of influence COI)? Many Thanks.
Hello all,
I have implemented UVM Register model. I am able to check the values at the Interface level, but i cannot see the register values in the UVM Register viewer.
Can anyone help me in fixing this issue?
Kindly waiting for your replies...
Thank you,
Best regards,
Meghana
Hi there, SystemVerilog community,
I would like to run several instances of a simulation, each with a separate include file rom a different path. I would like to hand a +define+FILEPATH to the simulation and use the in the line, where I include the files. Now, what I have found out is, that an "include" directive cannot resolve macros. Is that correct? Is there a way around it? Do you have any suggestions?
Example with code:
call simulation with +define+FILEPATH "/.../..."
then use:
`include FILEPATH
-> can't be done.
Thank you for any help on this.
Michael
Hi everyone,
I'm new to scripting and so far it has been really overwhelming.
I want to run a tcl file using a command directive in Xcelium, and so far i've had no luck. The tcl file was initially made for modelsim so it contains commands like vlog (verilog compiling) and vsim (verilog simulation invoking) . It works fine for Modelsim as i just enter the command "do sim.tcl' and it runs smoothly. I'm yet to find alternative commands to these in Xcelium. Also, i'm not directly using a linux computer. I'm connected to the linux computer database system through the internet and i have no visuals, only the command line.
It would be really appreciated if someone can guide me. Sorry if the question is very lame.
Regards,
A