Hi all,
I have the extracted view of a 32-bit adder in subthreshold. Is there any tool in cadence to check the yield of the circuit?
ThANKS,
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adder functional verification
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IMC tool is not mergeing properly already merged coverage files
HI,
I have 9000 test cases so I am running tests in batch of 1000 with coverage enabled and merging them using imc batch command. Till this point it is working in fatastic way. But when I am trying to merge "already merged" coverage .icc , it is merging but coverage numbers are getting reduced comapred to older merged coverage number.
Do we have any limitation or rule how to merge?
IMC tool version : MDV1710
Thanks
Sushant
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Support VHDL2008 in ncsim
Hello,
Which option enables support of VHDL2008 in ncsim ?
Thanks.
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How to export searched signal list using simvision design search to a text file?
Hi,
I am using Simulation Analysis Environment SimVision(64) 15.20-s025. I have a list of signals searched and displayed using the design search window and I cant seem to find a way to export them to a text file. Is there a way to do this?
Thanks.
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Merging data base with two RTL changes
Hi team,
Do we have any provision to merge two different version of coverage .icc files?
Example. I have generated coverage data base D1 with RTL changeset CL1. There are some changes done in RTL so coverage data base D2 regerated on RTL changeset CL2 . Does IMC provides any provision to merge D1 and D2?
I have tried running imc in batch mode with merge command but it is giving error.
IMC version : cadence/MDV1710
Thanks
Sushant
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Is ncsim (version 12.10-s19) fully compatible with VHDL2008
Hello,
When compiling VHDL source with option -V200X, I get error on this line:
pixel_new := (others=>'0') when lfsr_val(15) else (others=>'1');
Any comments.
Thanks.
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Force X in gate level simulation
How to initialize flops not having reset pin in gate level simulation?
I expected -ncinitialize to do. but it doesn't.
What is the best (simple) and general way for cadence simulator ?
Thanks in advance.
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UVM RAL
I am using Cadence register model. I am trying to randomize a register within model with constraint.
assert( reg_model_hanldle.reg_name.randomize() with { fieldname.value == 'habcd});
I get an error indicating fieldname is not a class item. Model is generated using Cadence tool .
How do I constraint randomize a register within a model?
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Show all drivers for a particular signal at a particular time in ncim
Hello,
The problem is expressed in subject: does exist some technique that allow to show all signal drivers at a particular time
Thanks in advance.
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Verifier Access to SV Variable in Testbench
I have a systemverilog testbench that simulates fine in Explorer. It contains a logic variable that indicates pass/fail of the test.
In Verifier, I can import the Maestro view as an implementation, but I can't find how to access the logic variable so that it can be verified against the specification.
How do I do this?
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Cadence iLS course manual refers to non-existent 'training' for learning how to use tool features
I am taking the course JasperGold Formal Fundamentals. The lab manual assigns tasks that say to use a feature of JasperGold shown in 'training'. I watched all the videos and they only introduce the area of formal verification, without demonstrating any features of JasperGold. The labs themselves don't explain how to use these features.
Due to this I am struggling to complete the labs.
Any help would be appreciated. Thanks.
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Collect only Covergroups
Hi,
i would like to collect functional coverage, but only the covergroup part. meaning i don't want to collect also data for assertions (ABV)
currently i am using the flag of " -coverage u " which collect both covergroups and assertions.
on the same topic, i am MSIE user. where should i locate this flags? only in simulation run? or should i add it also to primary and incremental runs?
Thanks,
Ariel
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Xcelium DPI
I am calling c functions from sv module. c functions are compiled in shared lib. I am able to call c function from sv module with shared lib.
I am using xcelium xrun for simulation. I want to use static lib instead of share lib for c functions. I am using gcc compiler to build shared and static lib.
Can I use static lib containing c functions and used with DPI?
Can you please give example to show how to compile using gcc and run using xrun?
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Is there a way to adapt vRfine file after RTL source file updated and line number changed
Hi,
In case of we have a vRefine file(eg: expression exclusion), and then RTL source file is modified which result in line number changing,
when we apply vRfine file in IMC, the exlusion can not be applied correctly because previous code line changed.
Does anyone know is there a way we can use to adapt vRfine file conveniently to avoid manual modification of vRfine file?
Thanks
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Array of covergroup not supported
I have defined a covergroup inside a package and creating instances of it in a class as shown below:
covergroup example_cg(bit en);
option.name = "ex_cg"; option.per_instance = 1;
ex_cp: coverpoint en;
endcovergroup
class ex_coverage_collector extends uvm_component;
.
..
example_cg ex_cg[4];
endclass
I am getting this error:
xmvlog: *E,CGIANS Arrays of covergroup instances are not supported
What is the best approach to create multiple covergroup without code replication?
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using eManager to read regression files but failed.
when i tried using eManager to read regression files but failed, so no data is available when click vplan button for verification plan map and code coverage analysis using IMC.
eManager's log is attached below. can anyone who had any experience on this help? thanks so much.
*** Warning: VM_UCM_FILE_READ_FAILED: Failed to read coverage model file /user/hxzh.tmp/20190513/nor_regression.hxzh.19_05_27_10_23_55_8052/testcase_model_28a5ee8a-8061-11e9-b383-bb4d3052dabc_nor_regression_default.ucm. Model skipped.
To change the severity, type:
set notify -severity=<new-severity-level> VM_UCM_FILE_READ_FAILED
To see possible severity levels use 'set notify -help'
*** Warning: VM_UCM_FILE_READ_FAILED: Failed to read coverage model file /user/hxzh.tmp/20190513/nor_regression.hxzh.19_05_27_10_23_55_8052/model_dir/icc_73072a11_5c7615b8.ucm. Model skipped.
To change the severity, type:
set notify -severity=<new-severity-level> VM_UCM_FILE_READ_FAILED
To see possible severity levels use 'set notify -help'
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using eManager to read regression files but failed.
when i tried using eManager to read regression files but failed, so no data is available when click vplan button for verification plan map and code coverage analysis using IMC.
eManager's log is attached below. can anyone who had any experience on this help? thanks so much.
=================
*** Warning: VM_UCM_FILE_READ_FAILED: Failed to read coverage model file /user/hxzh.tmp/20190513/nor_regression.hxzh.19_05_27_10_23_55_8052/testcase_model_28a5ee8a-8061-11e9-b383-bb4d3052dabc_nor_regression_default.ucm. Model skipped.
To change the severity, type:
set notify -severity=<new-severity-level> VM_UCM_FILE_READ_FAILED
To see possible severity levels use 'set notify -help'
*** Warning: VM_UCM_FILE_READ_FAILED: Failed to read coverage model file /user/hxzh.tmp/20190513/nor_regression.hxzh.19_05_27_10_23_55_8052/model_dir/icc_73072a11_5c7615b8.ucm. Model skipped.
To change the severity, type:
set notify -severity=<new-severity-level> VM_UCM_FILE_READ_FAILED
To see possible severity levels use 'set notify -help'
*** Warning: VM_UCM_FILE_READ_FAILED: Failed to read coverage model file /user/hxzh.tmp/20190513/nor_regression.hxzh.19_05_27_10_23_55_8052/model_dir/icc_73072a11_5c7615b8.ucm. Model skipped.
To change the severity, type:
set notify -severity=<new-severity-level> VM_UCM_FILE_READ_FAILED
To see possible severity levels use 'set notify -help'
*** Warning: VM_UCM_FILE_READ_FAILED: Failed to read coverage model file /user/hxzh.tmp/20190513/nor_regression.hxzh.19_05_27_10_23_55_8052/model_dir/icc_73072a11_5c7615b8.ucm. Model skipped.
To change the severity, type:
set notify -severity=<new-severity-level> VM_UCM_FILE_READ_FAILED
To see possible severity levels use 'set notify -help'
*** Warning: VM_UCM_FILE_READ_FAILED: Failed to read coverage model file /user/hxzh.tmp/20190513/nor_regression.hxzh.19_05_27_10_23_55_8052/model_dir/icc_73072a11_5c7615b8.ucm. Model skipped.
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Power Quality Requirements
Folks,
I am new here but looking for expert guidance on power quality requirements for the Palladium Z1 XL?
Have been asked to consider plugging these in directly to grid power without conditioning. What are the voltage tolerances and durations before we start noticing issues?
I have seen voltage sag for up to 66% for 4 cycles for normal utility power.
Thanks,
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xmelab: *E,CUVDNF (./netlist.vams,1748|8): Could not determine discipline for this expression
Hey experts,
We are facing an error while running xrun for simulation of netlist:
<SomeModule> <SomeModuleInstance> ( .() ..........
xmelab: *E,CUVDNF (./netlist.vams,1748|8): Could not determine discipline for this expression
I wanted to know what is the meaning of this violation and what might be a tentative fix. I have already made sure that this module is present in filelist.f.
Thanks,
Abhishek
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How to netlist a VHDL-AMS generic of type "time" correctly in ADE?
Hi,
while trying to transfer a working mixed-signal system model from Mentor Graphics SystemVision to Cadence Virtuoso/AMSDesigner I came across the following problem.
Some of the VHDL-AMS components in my system model include generic parameters of type "time", for example:
entity comparator_d is
generic (
delay : time := 1.0 us;
hysteresis : voltage := 0.0
);
port (
terminal in_pos : electrical;
terminal in_neg : electrical;
signal output : out std_logic := '1'
);
end comparator_d;
I let Virtuoso (v6.1.8) create a schematic symbol from this code, then I instantiated the symbol on a new schematic with all generics left at their default values. When I netlist the design in ADE with the simulator set to "ams", the following netlist entry is created:
comparator_d #(.delay("1.0 us")) I10 (.\output ( net1 ), .in_pos( net2 ), .in_neg( net3 ));
The time value 1.0 us is passed as a string, which is not recognized as a valid time specification by the simulator.
Warning from spectre in
`classd_models__shell_model__schematic__0x10000001':`shell_model',
during hierarchy flattening.
WARNING (SFE-30):
"/home/hennig/sim/classd/shell_model/ams/config/netlist/netlist.vams"
28: shell_model.I10: `DELAY' is not a valid parameter for an instance
of `CLASSD_MODELS__comparator_d__behavioral__0x10000001'. Ignored.
If I change the CDF parameters of the delay property so that the value is parsed as a number, I can change the netlist entry into something like this, ....
comparator_d #(.delay(1.0e-6)) I10 (.\output ( net1 ), .in_pos( net2 ), .in_neg( net3 ));
..., but then the simulator complains about a type mismatch.
Do you have any suggestions how to pass generics of type "time" correctly through a Verilog netlist to a VHDL-AMS component?
Thanks,
Eckhard
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