Hello,
I'm working on creating a robust simulation environment for a project and I'm not super familiar with Simvision/Incisive. In modelsim you can view the values inside task calls the same way you view signals in modules. Is there a way to do this in Simvision? I'm thinking maybe it has to do with the $shm_probe command. I'm doing $shm_probe(name, "ACM").
Is this possible with the Cadence tools?
Thank you,
Dylan
Hi,
I'm using NCSIM v15.20.030 version.
Have you seen the below issue while running regression with NCSIM; If so please share your feedback.
irun: *W,WKWTLK: Waiting for a Exclusive lock on file '/home/*/run/INCA_libs/irun.lnx86.15.20.nc/.ncrun.lock'. pid:120971
With the above error,the test couldn’t execute and went to block state.
Please help in this regard?.
Thanks,
Regards,
Mahee.
Hi all,
Anyone know how to define library in cds.lib?
Thanks and regards,
Yu
I would like to print "obj" or "obj.m_name" every time the following UVM code line is hit. What should I pass to the -exec switch to make this happen?
stop -create -line 308 -file $UVM_HOME/src/base/uvm_heartbeat.svh -all -exec {value obj}
The obvious attempt: "value obj", produces an error:
ncsim: *E,PNOOBJ: Path element could not be found: obj.
Hi Cadence,
I use irun(64): 15.20-s029 to run some SV files I fetched from the internet.
I am getting this error but it seems those are correct syntax in Verilog 2001 and later.
How do I fix those?
Thank you!
file: ../tb/tnoc/rtl/bcm/tbcm_counter.sv
localparam int WIDTH = $clog2(MAX_COUNT + 1)
|
ncvlog: *E,LOCALP (../tb/tnoc/rtl/bcm/tbcm_counter.sv,6|11): illegal localparam in list of parameters [12.2(IEEE-2001)].
module gncorelib.tbcm_counter:sv
errors: 1, warnings: 0
module tbcm_counter #(
parameter int MAX_COUNT = 3,
parameter int MIN_COUNT = 0,
parameter int INITIAL_COUNT = MIN_COUNT,
parameter bit WRAP_AROUND = 1,
localparam int WIDTH = $clog2(MAX_COUNT + 1)
)(
input logic clk,
input logic rst_n,
input logic i_clear,
input logic i_set,
input logic [WIDTH-1:0] i_set_value,
input logic i_up,
input logic i_down,
output logic [WIDTH-1:0] o_count,
output logic [WIDTH-1:0] o_count_next
);
localparam bit [WIDTH-1:0] INITIAL = INITIAL_COUNT;
localparam bit [WIDTH-1:0] MAX = MAX_COUNT;
localparam bit [WIDTH-1:0] MIN = MIN_COUNT;
logic [WIDTH-1:0] count;
logic [WIDTH-1:0] count_next;
xcelium> run -step
../uvm-1.2/src/base/uvm_objection.svh:829 comp.raised(this, source_obj, description, count);
xcelium> value this
xmsim: *E,PNOOBJ: Path element could not be found: this.
Thanks,
Avidan
Hello all... I am the sysadmin at my place of work, i do not know how these tools work, i just install them for our engineers.
I just tried to install via iscape 4.2, XceliumMain_18.09. The install works well until the end where it indicates the config failed, see below email i received after the install finished...
What do i need to do to resolve this?
Thanks...
nstallScape 04.23.s10
Platform: lnx86
Process finished on Wed Jan 23 11:47:01 EST 2019.
Release: XCELIUMMAIN_18.09.008_lnx86
Operation: Download and Install
Download Directory: /data/tmp/cadence/downloads
Install Directory: /data/eda/Cadence/XCELIUM1809
Download Status: Success
Install Status: Success
Configure Status: Failed
I read the article of John Brennan "A Coverage Time-Saving Tip" of 20 Nov 2015 in the Blog section and hoped to solve the problem that after design updates I do not have to fully evaluate set up the refinement files
I put the "set_refinement_resilience setting" in the .ccf files I use during regressions but this does not solve the problem that I nearly have to re-evaluate my refinement files.
So my question is what are the steps to be taken to prevent that I have to setup the excludes in my refinement files, apparently setting the "set_refinement_resilience" setting in the .ccf files is by far not enough.
Off course it is clear that the excludes connected to removed/updated code should be removed and/or updated but I hoped to see that excludes which are connected to shifted could be easily re-used.
I am using imc:
In simvision how to reinvoke a simulation when some testbench code is changed such that the changes are included after the reinvoke ?
Thanks in advance!
Is there a way to generate coverage reports, not in ucd or any other format. I have written basic covergroup and passed arguments[-covoverwrite -cov_cgsample -cov_debuglog -coverage u] to the xrun command, however I don't see anything in sim directory, nor do I see anything in the logs indicating the covergroups have been hit. How can I confirm that cover groups are getting hit and essentially observe the bins. In Questa sim, you essentially get them as part of the log itself.
Hi,
I've a below typedef definition;
typedef enum {SP_FS='h00, LP_ID_END='h37, LP_RESERVED='h3F} DT_DATA_TYPE;
The above typedef has been used in our RTL design files as below;
DT_DATA_TYPE curr_pd;
assign curr_pd = DT_DATA_TYPE'(data_type); // input [5:0] data_type; input to the module
After compiling the design file; I've got the below error;
DT_DATA_TYPE curr_pd;
|
ncvlog: *E,ILLPDL (../../../../axi_mipi_receiver_dphy_new/rtl/append_extra_bytes.sv,69|21): Mixing of ansi & non-ansi style port declaration is not legal.
I don't understand the above issue and is working fine in other EDA tools. Please help in this regard?...
I'm using Incisiv 15.20.026 version.
Thanks,
Mahesh.
I have a group of covergroups which may or may not hit during a regression run. I want a refinement file which looks at these covergroups together and excludes the ones which don't get hit. Is it possible to have a smart refinement file?
ncvlog: *E,DLCIRD
what was the meaning of this error and help me to resolve this issue.
covergroup cg @(posedge clk);
a: coverpoint v_a
{..}
b: coverpoint v_b
{..}
c:coverpoint v_c
{..}
combinedCovepoint: [How]??
endgroup
I have 3 coverpoints a,b & c. They all have 1 bin only. Now I want to create another coverpoint which reports 100% if any of them{a,b,c} get a hit. I believe this cannot be done via cross. Is there a way to do this?
Hi,
I am trying to rum my simulation without
\-uvmnoautocompile \ and uvm 1.2
Version : irun(64): 15.20-s030: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
I am getting the error message.
ncvlog: *E,UNDIDN (/pkg/cadence-incisiv-/15.20.030/i686-linux/tools/methodology/UVM/CDNS-1.1d/additions/sv//cdns_recording.svh,79|16): 'm_handles': undeclared identifier [12.5(IEEE)].
ncvlog: *E,DLCSMD: Dependent checksum verilog_package worklib.cdns_assert2uvm_pkg:sv (VST) doesn't match with the checksum that's in the header of: verilog_package worklib.cdns_uvm_pkg:sv (VST).
irun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).
irun: *E,UVMCXF: The process to compile the uvm extensions has failed. Add -uvmnocdnsextra to disable the addon package or point to the right version using -uvmexthome.
Reading from this blog it states that cadence transaction recording is written with version 1.1d.
I dont want to revert to 1.1d since some VIP that i am using are not backward compatiable.
Is it solved or re-written in later version?
Regards.
I have added some coverpoints to my testbench, which hare getting sampled at every posedge. This has increased my simulation time 10x time. Is this a fairly likely occurrence? Or, there is a way to optimize this.
Hello All,
I am a new starter for Cadence flow, now i have a legacy project which using Incisiv.
According to handover doc, the flow i am using is:
1. Use emanager to run regression using a vsif file, and then it will generate a vsof file.
2. Launch vplan tree window from emanager, and read vplan file.
3. Publish report using "reports" button in vplan tree GUI. (the report include 3 part: test feature/code cov/functional cov)
4. Launch IMC from vplan tree GUI, and get .vRefine file in IMC.
My question is:
How can we apply vRfine file to vplan tree GUI so that we can generate report with vplan tree after applying it?
Hi,
I am trying to disable VHDL assert but I was not able to find the option used by xrun to do that.
Anyone can help ?
Thanks.
Nabil
PS: following an example of the code implemented and its message:
assert(now - timeADXC >= tAVAV)
report "(Address valid to next address valid time violation (tAVAV = 70/90 ns) !!)"
severity warning;
ASSERT/WARNING (time 8329528909571 FS) from process testbench.prom_NCS0_1:timingCheck_process (architecture work.m29w800d_msb:behavior)
(Address valid to next address valid time violation (tAVAV = 70/90 ns) !!)
Hi Experts,
If there is a feature in SimVision that i can export all the loads of one signal.
Thanks
Hi,
I am using nclaunch in IES sometimes to debug some compile scripts by checking compilation content.
Is there any alternative in Xcelium 18.09 for nclaunch? (nclaunch: command not found)
BR
Michael