While placing parts, I cannot find a part which I can use to simulate 2 inductors in mutual induction with each other. Is anything similar there? I feel like this software was created with the idea of giving utmost pain to the users.
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Any symbol for simulation of mutual induction between two inductors?
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Generation of EVCD file for Verilog-AMS
Hi,
Testbench developed in verilog-AMS and uses wreal as a ports and internal signals.
When It's tried to generate EVCD for design ports with $dumpports() gives error related to "Wreal is not supported".
I am using IUS 10.2 version. I need EVCD for vector generation for tester.
Please help me out.
Thanks in advance.
Regards,
Ankit
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irun 11.10-s062 -R option and *W,WKWTLK "Waiting for a Exclusive lock"
My company recently upgraded from IUS 10.2 to 11.10. Our sim-regression suite uses the strategy of compiling a snapshot once (irun), then using that snapshot to run many different sim testcases in parallel (irun -R).
With IUS 10.2, we had no trouble with kicking off multiple simjobs simultaneously,from the same INCA_libs dir.
Now, with IUS 11.1, we're getting some kind of file-locking warning whenever more than 1 job is started from the snapshot. Basically, if I kick off 30 simjobs in parallel, they run serially (one most complete before the next one starts.) So we are unable to simulate in parallel unless we compile each testcsae in its own separate directory.
irun: *W,CSSF: HDL source files with -R option will be ignored.
irun: *W,WKWTLK: Waiting for a Exclusive lock on file '/.../mysim/INCA_libs/irun.lnx86.11.10.nc/.ncrun.lock'. pid:2266.
I'm confused. I thought using the '-R' option tells irun *NOT* to reocmpile anything. So why does IUS 11.1 still trying to lock files?
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Use of a specify block within a SystemVerilog interface
Hi All,
I'm currently converting a legacy testbench to use SystemVerilog interfaces between the DUT and some behavioural models. The testbench code includes a specify block that uses the $width system task to check for glitches on a signal between the DUT and one of the models.
I've tried to update the code so that the $width task now checks the equivalent signal within the interface instance, which connects the DUT and the model. For example:
specify
$width(posedge interface_inst.my_signal, 100, 0, my_notifier);
endspecify
Unfortunately Incisive reported a ncvlog error (ILLHIN) for the line containing the $width task call:
"A hierarchical name was used as an identifier where a hierarchical name is not allowed. Use a simple identifier."
I then moved the specify block to the interface itself, as on reflection, this seems a more suitable place anyway. The specify block is defined within the scope of the interface declaration. For example:
interface my_interface ();
logic my_signal, ...etc
modport ( ...);
specify
$width(posedge my_signal, 100, 0, my_notifier);
endspecify
endinterface
This time, Incisive reported a different ncvlog error (DECINM) for the line containing the specify keyword:
"The declaration is only valid within a module, interface, and program and not supported within task, function and package."
The message clearly states that a specify block within an interface is supported so why is Incisive reporting an error?
Thanks in advance for any help.
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XBus XSoC XSerial examples
In INCISIV 10 and above where to find xbus,xsoc and xserial examples??![]()
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print all the `defines
Hi is there a way to print all the macros? we've got a sim env where macros are defined from command line, verilog and specman files. i am looking for a way to list all of the `define during simulation
thx
dean
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list generation
Hi,
I use the following code:
var list : list of uint (bits:14);gen list keeping {
it.size() == list_size_parameter;
it.all_different(it);
};
to gen a list of indices, the size of a given parameter.
list size can be up to 20K, and I get a WARN_GEN_BIG_LACE as a consequence.
what may be the preferrabe way to do this in regards to memory and cpu resources?Thanks
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time between two events
Hi all is there any way by which i can measure time between two events (Specman e code)??
e.g. time between two resets
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Specman Tutorial
Hi everybody ,
Can anybody please suggest me quickstart tutorial to specman-e . I have knowledge of systemverilog uvm and now i want to shift to specman e. I Have specman 9.2 and above... are there any tutorials provided by cadence with the tools???
Thanks and regs,
Pravin
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How to match the UVC version & the cdn_e_utils version
Hi,
When I try running the example tests from /vr_ahb/examples/sv/regular_env, I see the following during the start of simulation & simulator hangs giving a pop-up window. And in the terminal I see the below message:
ncsim> INTERNAL ERROR - VIPP1035
.Please make sure your UVC version is compatible with the cdn_e_utils version
From the irun.log I see the UVC version as "UVC version: 11.30.001-p" .
And in the file /utils/cdn_e_utils/PACKAGE_README.txt I see the following:
* Title: Cadence E Utils
* Name: cdn_e_utils
* Version: 11.30.007-s
* Modified: 13-Dec-2011
* Category: UVC
* Support: support@cadence.com
* Documentation:
See Cadence Help for VIPP documentation
% <install_dir>/tools/bin/cdnhelp
* Release notes:
See VIPP Release_Notes.pdf at
<install_dir>/Release_Notes.pdf
* Demo:
To run the demo use the next command:
cdn_e_utils/demo.sh
For more information for demo.sh flag use:
cdn_e_utils/demo.sh -h
So how to upgrade my UVC version to match the cdn_e_utils. Please help.
Regards
Giri
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Switch to run through assertions
Sim Vision is halting my simulation when an assertion fires, is there a way to force the simulator to fire the assertion but continue running.
I have tried this switch(-assert_logging_error_off) which seemed correct but It didnt work
Most of the switches I have tried completely disable the assertions.
Any assistance would be appreciated
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Viewing dynamic objects in the Simvision waveform window
Hi All,
I'm having trouble displaying the value of class data members in a Simvision waveform window (currently using version 12.10-s006).
I'm using irun interactively to run my simulations, so I invoke irun with the following options:
irun -gui -access +rwc -linedebug ...etc
My testbench is UVM based so I use the UVM factory to build a simple test object.
At time 0 ns, I can see my classes in the SystemVerilog Class Browser, but there are no objects displayed (as the factory hasn't built them yet). I then run my simulation for 1 ns and I can then see an object displayed for the class containing the data member I'm interested in. Having clicked on the object (5854_1), it is then displayed in the design browser as @5854_1. I can expand the object to show the data member and I can right click the mouse to select the 'Create Probe ...' menu option.
Having created a probe, the data member is displayed in my waveform window, but when I then run my simulation to the end, no waveform is displayed and its value is displayed as "No Value Available".
Has anyone got any idea why my data member has no waveform?
Thanks for any help!
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irun: design.v is verilog and verilog AMS
Hi,
We are migrating to an irun based flow to simplifiy our compile/elab/sim flow, and have a slight issue.
We have a file design.v, containing module design. Depending on a define, this can either be a standard digital module, or a WREAL model.
i.e. Within the file
`ifdef WREAL
wreal sig_name;
`endif
This issue is that irun uses the file extesion to infer the type of file, in this case, it does not work.
This is a non-trivial design, so I have multiple verilog, vhdl and vams files, and using the -ams is probably not an option.
Question is: Can anyone suggest a solution? Is there an command line option that I missed, which applies to a single file only?
Thaks,
Steven
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UNDERSTANDING CADENCE JTAG VIP DEMO
Hi ,
I have run the JTAG VIP demo in sv lang . while running the demo the design browser shows : the top tb file , jtag if , sys hierarchy , packages and ovm top levels .
1)what is the SYS hierarchy ? when we close the simvision console after creating .shm and try to load the .shm it does not shows the sys hier that time while for other demos ex: apb it shows intf as well as ovm_hier ?
2)also there is some problem in loading transactions which are under the sys->master_agent->monitor transations. i mean the transactions are not created. why the master and slave agents are under sys ?
3)finally for understanding the JTAG environment what transactions we have to check apart from top jtag signals and intf signals ?
Please help me out with my doubts as i am new to verification .
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How to get the activity power in Simvision
Dear all,
I'm using simvision to analysis activity power.
Here is the command I used:
read_vcd -vcd_module dut -module top -activity_profile -start_time 10000 -end_time 30000 -simvision ../../i303_tb/test/TOP_IO_Power_exper/POWER_EXPER.vcd
So, how can I see the activity power in the waveform?
In other words, I want see the active power during the signal changed in waveform.
Thanks for the help ^_^.
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How to Compile System Verilog
Hi,
I use ncverilog: 05.70-s015: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
TOOL: ncverilog 05.70-s015:
and foll switches
-update
+access+r
+sv31a
I egt the foll errs
class mem_base_object;
|
ncvlog: *E,EXPMPA (../models/mem_base_object.sv,3|4): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
(`include file: ../models/mem_base_object.sv | line 3, `include file: ../models/memory_top.sv line 3, file: ../tb/memory_tb.sv line 4)
mem_txgen txgen;
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ncvlog: *E,ILLPDL (../models/memory_top.sv,11|16): Mixing of ansi & non-ansi style port declaration is not legal.
(`include file: ../models/memory_top.sv line 11, file: ../tb/memory_tb.sv line 4)
mem_scoreboard sb;
pls let me know a solution
Thanks
Chandra
Force10 Networks Inc, SJC
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Package monitor_pkg could not be bound.
Hi I am using IES to compile system verilog classes and files:
I am getting this error during compilation:
cvlog: *E,NOPBIND (/proj/kunal/monitor_pkg.sv,10|28): Package monitor_pkg could not be bound.
import monitor_pkg::*;
Am, I missing some option at command line or some this need to be done....
Regards
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electronics circuits opearation
is it possible to bring node voltage value as a resistor element value in pspice?justify.![]()
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Facing Error while running specman test
Hi,
I am facing the below error when i run the specman test,please do let me know is this problem w.r.t environment variable settings.
Compiler version D-2009.12-2_Full64; Runtime version
D-2009.12-2_Full64; Nov 2 16:19 2012
failed to dlopen
/apps/cds/incisiv/9.20.033/SPMN92/specman/linux64/libsn_mm.so:
/apps/cds/incisiv/9.20.033/SPMN92/specman/linux64/libsn_mm.so: undefined
symbol: sn_global_method_indices
D-2009.12-2_Full64; Nov 2 16:19 2012
failed to dlopen
/apps/cds/incisiv/9.20.033/SPMN92/specman/linux64/libsn_mm.so:
/apps/cds/incisiv/9.20.033/SPMN92/specman/linux64/libsn_mm.so: undefined
symbol: sn_global_method_indices
Regards
kaleem.
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View memory in NC-Verilog
Hi guys,
I'm working on FPGA simulation.
I want to see the data in memory unit (BlockRAM), could anyone tell me where I can find the memory view in NC-Verilog.
Thanks.
-Rohs
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