Hi Friends,
I developed AHB arbiter UVC in sv by using UVM methodology. Now i want to verify my arbiter uvc with cadence ahb vip in e environment.while integrating i am facing error and then simulation stops.
I have created files...
1. file name: arbiter_dut_top.v
module arbiter_dut_top(
// arbiter input signals ,
// arbiter output signals
)
// input declarations
// output declarations
arbiter_interface arb_if(hclk,hreset) ;
assign arb_if.htrans =htrans ; // for input signal
assign hmaster =arb_if.hmaster ; // for output signal
endmodule
2. file name: ahb_arbiter_tb.v
module ahb_arbiter_tb();
// here all the signals are connected to e top file
// variable declaration
master_mux m_mux(
)
slave_mux s_mux(
)
arbiter_dut_top A_dut(
)
endmodule
3. file name : vr_ahb_config_arbiter.e
// in this file i disable the cadence arbiter uvc and active the remaing uvc's
// i made name of env as ARB_DUT
// connected all the agents through synchronizer
extend ARB_DUT vr_ahb_env {
keep has_active_masters ;
keep not has_passive_masters ;
keep has_active_slaves ;
keep not has_passive_slaves ;
keep has_passive_arbiter ;
keep not has_active_arbiter ;
keep has_active_decoder
};
extend ARB_DUT vr_ahb_env {
keep soft num_active_masters == 2;
keep soft num_active_slaves == 4;
keep has_active_masters_names =={M2; M4};
keep has_active_slaves_names == {S1;S2;S3;S4} ;
};
// vr_ahb_signal_map for all the uvc's interface signals
Finally, I integrated my arbiter uvc in cadence ahb vip(e environment). cadence arbiter is passive, my arbiter is active. But,simulating and it structs and showing error as " it is a dut error because of hgrant0". when i open the GUI, once i checked my arbiter interface signal grant, hmaster and hmasterlock signals as 'X'.
Can any one help me what is the reason for it?If any one knows the other way of integration tips,please share with me.
Thanks,
k@nth
![]()